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| Data Sheet August 2001 ORCA(R) ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver Introduction Field-programmable system chips (FPSCs) bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single device. Agere Systems Inc. has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. Built on the Series 4 reconfigurable embedded system-on-chips (SoC) architecture, the ORT8850 family is made up of backplane transceivers containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used) full-duplex synchronous interface, with built-in clock and data recovery (CDR) in standard-cell logic, along with up to 600K usable FPGA system gates. The CDR circuitry is a macrocell available from Agere's Smart Silicon macro library, and has already been implemented in numerous applications including ASICs, standard products, and FPSCs to create interfaces for SONET/SDH STS-3/ STM-1, STS-12/STM-4, STS-48/STM-16, and STS192/STM-64 applications. With the addition of protocol and access logic such as protocol-independent framers, asynchronous transfer mode (ATM) framers, packet-over-SONET (POS) interfaces, and framers for HDLC for Internet protocol (IP), designers can build a configurable interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge using our PCI soft core. The ORT8850 family offers a clockless high-speed interface for interdevice communication, on a board or across a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET application, all SONET functionality is hidden from the user and no prior networking knowledge is required. The 8850 also offers 8B/10B coding in addition to SONET scrambling. Also included on the device are three full-duplex, highspeed parallel interfaces, consisting of 8-bit data, control (such as start-of-cell), and clock. The interface delivers double data rate (DDR) data at rates up to 311 MHz (622 Mbits/s per pin), and converts this data internal to the device into 32-bit wide data running at half rate on one clock edge. Functions such as centering the transmit clock in the transmit data eye are done automatically by the interface. Applications delivered by this interface include a parallel backplane interface similar to the recently proposed RapidIOTM packet-based interface. Table 1. ORCA(R) ORT8850 Family--Available FPGA Logic Device ORT8850L ORT8850H PFU Rows 26 46 PFU Columns 24 44 Total PFUs 624 2024 FPGA User I/O 296 536 LUTs 4,992 16,192 EBR Blocks 8 16 EBR Bits (K) 74 147 Usable Gates (K) 260--470 530--970 Note: The embedded core and interface are not included in the above gate counts.The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25K gates. 7K gates are used for each PLL and 50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate calculations. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Table of Contents Contents Page Contents Page Introduction..................................................................1 Embedded Core Features (Serial)...............................4 Embedded Core Features (Parallel)............................4 Programmable FPGA Features ...................................5 Programmable Logic System Features .......................6 Description...................................................................7 What Is an FPSC? ...................................................7 FPSC Overview .......................................................7 FPSC Gate Counting ...............................................7 FPGA/Embedded Core Interface .............................7 ORCA Foundry Development System .....................7 FPSC Design Kit ......................................................8 FPGA Logic Overview ..............................................8 PLC Logic ................................................................8 Programmable I/O ....................................................9 Routing .....................................................................9 System-Level Features..............................................10 Microprocessor Interface .......................................10 System Bus ............................................................10 Phase-Locked Loops .............................................10 Embedded Block RAM ...........................................10 Configuration ..........................................................11 Additional Information ............................................11 ORT8850 Overview ...................................................12 Device Layout ........................................................12 Backplane Transceiver Interface ...........................12 HSI Interface ..........................................................15 STM Macrocell .......................................................15 8B/10B Encoder/Decoder ......................................15 FPGA Interface ......................................................15 Byte-Wide Parallel Interface ..................................15 FPSC Configuration ...............................................16 Generic Backplane Transceiver Application..............17 Synchronous Transfer Mode (STM) .......................17 8B/10B Mode .........................................................17 Backplane Transceiver Core Detailed Description ....18 HSI Macro ..............................................................18 STM Transmitter (FPGA AE Backplane) .................20 STM Receiver (Backplane AE FPGA) .....................23 8B/10B Transmitter (FPGA AE Backplane) ............30 8B/10B Receiver (Backplane AE FPGA) ................30 Pointer Mover Block (Backplane AE FPGA) ...........31 Receive Bypass Options and FPGA Interface .......33 Powerdown Mode ................................................. 33 STM Redundancy and Protection Switching ......... 33 LVDS Protection Switching ................................... 34 RapidIO Interface to Pi-Sched.................................. 34 Overview ............................................................... 34 Receive Cell Interface ........................................... 34 Transmit Cell Interface .......................................... 36 Memory Map............................................................. 38 Definition of Register Types .................................. 38 Absolute Maximum Ratings...................................... 55 Recommended Operating Conditions ...................... 55 Power Supply Decoupling LC Circuit........................ 56 HSI Electrical and Timing Characteristics ................ 57 Parallel RapidIO-like Interface Timing Characteristics......................................................... 58 Embedded Core LVDS I/O ....................................... 59 LVDS Receiver Buffer Requirements .................... 60 Input/Output Buffer Measurement Conditions (on-LVDS Buffer)..................................................... 61 LVDS Buffer Characteristics..................................... 62 Termination Resistor ............................................. 62 LVDS Driver Buffer Capabilities ............................ 62 Pin Information ......................................................... 63 Package Pinouts ................................................... 77 Package Thermal Characteristics Summary .......... 105 JA ..................................................................... 105 JC ..................................................................... 105 JC ..................................................................... 105 JB ..................................................................... 105 FPSC Maximum Junction Temperature .............. 105 Package Thermal Characteristics........................... 106 Package Coplanarity .............................................. 106 Package Parasitics ................................................. 106 Package Outline Diagrams..................................... 107 Terms and Definitions ......................................... 107 Package Outline Drawings ..................................... 108 352-Pin PBGA ..................................................... 108 680-Pin PBGAM .................................................. 109 Hardware Ordering Information .............................. 110 Software Ordering Information ............................... 111 2 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Table of Contents (continued) List of Figures Page List of Tables Page Figure 1. . ORCA ORT8850 Block Diagram .............13 Figure 2. . High-Level Diagram of ORT8850 Transceiver ............................................................14 Figure 3. . 8850 with 8B/10B Coding/Decoding ........18 Figure 4. . HSI Functional Block Diagram ................19 Figure 5. . Byte Ordering of Input/Output Interface in STS-12 Mode .....................................................20 Figure 6. . SPE and C1J1 Functionality ....................26 Figure 7. . SPE Stuff Bytes .......................................27 Figure 8. . Interconnect of Streams for FIFO ............28 Figure 9. . Example of Inter-STM Alignment ............28 Figure 10. . Example of Intra-STM Alignment ..........28 Figure 11. . Example of Twin STS-12 Stream ..........28 Figure 12. . Examples of Link Alignment ..................29 Figure 13. . Pointer Mover State Machine ................32 Figure 14. . RapidIO Receive Cell Interface .............35 Figure 15. . RapidIO Transmit Cell Interface ............36 Figure 16. . Sample Power Supply Filter Network for Analog HSI Power Supply Pins ........................56 Figure 17. . Receive Parallel Data/Control Timing ...58 Figure 18. . Transmit Parallel Data/Control Timing ..58 Figure 19. . ac Test Loads ........................................61 Figure 20. . Output Buffer Delays .............................61 Figure 21. . Input Buffer Delays ................................61 Figure 22. . LVDS Driver and Receiver and Associated Internal Components ...........................62 Figure 23. . LVDS Driver and Receiver ....................62 Figure 24. . LVDS Driver ..........................................62 Figure 25. . Package Parasitics ..............................106 Table 1. . ORCA ORT8850 Family-- Available FPGA Logic ................................................1 Table 2. . Transmitter TOH on LVDS Output (Transparent Mode) .................................................22 Table 3. . Transmitter TOH on LVDS Output (TOH Insert Mode) ...................................................22 Table 4. . Receiver TOH (Output Parallel Bus) ...........25 Table 5. . SPE and C1J1 Functionality .......................26 Table 6. . Valid Special Characters .............................30 Table 7. . Valid Starting Positions for an STS-Mc .......31 Table 8. . RapidIO Signals to/from FPGA ...................37 Table 9. . Signals Used as Register Bits ....................38 Table 10. . Structural Register Elements ...................39 Table 11. . Memory Map .............................................40 Table 12. . Memory Map Descriptions .......................45 Table 13. . Absolute Maximum Ratings ......................55 Table 14. . Recommended Operating Conditions ......55 Table 15. . Absolute Maximum Ratings ......................57 Table 16. . Recommended Operating Conditions ......57 Table 17. . Receiver Specifications ............................57 Table 18. . Transmitter Specifications ........................57 Table 19. . Synthesizer Specifications ........................57 Table 20. . Parallel Receive Data/Control Timing .......58 Table 21. . Transmit Parallel Data/Control Timing ......58 Table 22. . Driver dc Data ...........................................59 Table 23. . Driver ac Data ...........................................59 Table 24. . Driver Power Consumption .......................59 Table 25. . Receiver ac Data ......................................60 Table 26. . Receiver Power Consumption ..................60 Table 27. . Receiver dc Data ......................................60 Table 28. . LVDS Operating Parameters ....................60 Table 29. . FPGA Common-Function Pin Description ........................................................63 Table 30. . FPSC Function Pin Description ................66 Table 31. . Embedded Core/FPGA Interface Signal Description ....................................................70 Table 32. . ORT8850H Pins That Are Unused in ORT8850L ...............................................................77 Table 33. . ORT8850L 352-Pin PBGA Pinout .............78 Table 34. . ORT8850L and ORT8850H 680-Pin PBGAM Pinout ...........................................88 Table 35. . ORCA ORT8850 Plastic Package Thermal Guidelines ...............................................106 Table 36. . ORCA ORT8850 Package Parasitics .....106 Table 37. . Device Type Options .............................. 110 Table 38. . Temperature Options .............................. 110 Table 39. . Package Type Options ........................... 110 Table 40. .ORCA FPSC Package Matrix (Speed Grades) ..................................................... 110 Agere Systems Inc. 3 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Embedded Core Features (Serial) s s s Implemented in an ORCA Series 4 FPGA. Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer. No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz--106 MHz clock, and a frame pulse. High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks. Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex). HSI function uses Agere's 850 Mbits/s serial interface core. Rates from 212 Mbits/s to 850 Mbits/s are supported directly (lower rates directly supported through decimation and interpolation). LVDS I/Os compliant with EIA(R)-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes. Low-power 1.5 V HSI core. Low-power LVDS buffers. Programmable STS-1, STS-3, and STS-12 framing. Independent STS-1, STS-3, and STS-12 data streams per quad channels. 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic. On-chip, phase-lock loop (PLL) clock meets B jitter tolerance specification of ITU-T recommendation G.958. Powerdown option of HSI receiver on a per-channel basis. Selectable 8B/10B coder/decoder or SONET scrambler/descrambler. HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state. Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates. In-band management and configuration through transport overhead extraction/insertion. s s Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted. Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks. Built-in boundry scan (IEEE (R)1149.1 JTAG). FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both SONET scrambling and 8B/10B modes. Optional ability to bypass alignment FIFOs. 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. STS-192 and above rates are supported through multiple devices. ORCA FPGA soft intellectual property core support for a variety of applications. Programmable STM pointer mover bypass mode. Programmable STM framer bypass mode. Programmable CDR bypass mode (clocked LVDS high-speed interface). Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels with redundancy on a single device. s s s s s s s s s s s s s s s s s Embedded Core Features (Parallel) s s s Three full-duplex, double data rate (DDR) I/O groups include 8-bit data, one control, and one clock. Each interface is implemented with LVDS I/Os that include on-board termination to allow long-haul driving of backplanes, such as the industry-standard RapidIO interface. External I/O speeds on DDR interface up to 311 MHz (622 Mbits/s per pin), with internal, singleedge data transferred at 1/2 rate on a 32-bit bus plus control. Automatic centering of transmit clock in data eye for DDR interface. Direct interfaces to Agere Pi-Sched (266 MHz DDR LVDS), Pi-X (128 MHz TTL), and APC (100 MHz TTL) ATM/IP switch/port controller devices. s s s s s s s 4 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Programmable FPGA Features s High-performance platform design: -- 0.13 m 7-level metal technology. -- Internal performance of >250 MHz. -- Over 600K usable system gates. -- Meets multiple I/O interface standards. -- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. Traditional I/O selections: -- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/ Os. -- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. -- Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. -- Two slew rates supported (fast and slew-limited). -- Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time. -- Fast open-drain drive capability. -- Capability to register 3-state enable signal. -- Off-chip clock drive capability. -- Two-input function generator in output path. New programmable high-speed I/O: -- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), ZBT, and DDR. -- Double-ended: LVDS, bused-LVDS, LVPECL. -- LVDS include optional on-chip termination resistor per I/O and on-chip reference generation. -- Customer defined: ability to substitute arbitrary standard-cell I/O to meet fast-moving standards. New capability to (de)multiplex I/O signals: -- New DDR on both input and output at rates up to 133 MHz (266 MHz effective rate). -- New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). s dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. -- Soft-wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing, which reduces routing congestion and improves speed. -- Flexible fast access to PFU inputs from routing. -- Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. s Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. SLIC provides eight 3-statable buffers, up to 10-bit decoder, and PAL(R)-like and-or-invert (AOI) in each programmable logic cell. Improved built-in clock management with dual-output programmable phase-locked loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 416 MHz. New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as: -- One--512 x 18 (quad-port, two read/two write) with optional built-in arbitration. -- One--256 x 36 (dual-port, one read/one write). -- One--1K x 9 (dual-port, one read/one write). -- Two--512 x 9 (dual-port, one read/one write for each). -- Two RAM with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). -- Supports joining of RAM blocks. -- Two 16 x 8-bit content addressable memory (CAM) support. -- FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9. -- Constant multiply (8 x 16 or 16 x 8). -- Dual variable multiply (8 x 8). Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded backplane transceiver blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device. 5 s s s s s s Enhanced twin-quad programmable function unit (PFU): -- Eight 16-bit look-up tables (LUTs) per PFU. -- Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. -- New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. -- New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU. -- 32 x 4 RAM per PFU, configurable as single- or Agere Systems Inc. s s ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Programmable FPGA Features (continued) s s Built-in testability: -- Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG). -- Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. -- TS_ALL testability function to 3-state all I/O pins. -- New temperature-sensing diode. New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers. Variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E4). New local clock routing structures allow creation of localized clock trees. New edge clock routing supports at least six fast edge clocks per side of the device New double-data rate (DDR) and zero-bus turnaround (ZBT) memory interfaces support the latest high-speed memory interfaces. New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal logic. ORCA Foundry 2000 development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis. Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed specifications for UTOPIA Level 4 for 10 Gbits/s interfaces. Two new edge clock routing structures allow up to seven high-speed clocks on each edge of the device for improved setup/hold and clock to out performance. s s s s s s Programmable Logic System Features s s s PCI local bus compliant for FPGA I/Os. Improved PowerPC(R)860 and PowerPC II high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded backplane transceiver blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. New embedded AMBATM specification 2.0 AHB system bus (ARM (R) processor) facilitates communication among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and backplane transceiver logic. New network PLLs meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-3/STM-1 applications. Flexible general-purpose PPLLs offer clock multiply (up to 8x), divide (down to 1/8x), phase shift, delay compensation, and duty cycle adjustment combined. s s s s s s 6 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver signals off-chip, this on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and accounted for in the ORCA Foundry Development System. Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multimaster 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic functions including the embedded block RAMs and the microprocessor interface. Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system. For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device. Description What Is an FPSC? FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of ASICs. FPSC Overview Agere's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the FPGA functionality is changed--all of the Series 4 FPGA capability is retained: embedded block RAMs, MPI, PCMs, boundary scan, etc. The columns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality. The embedded cores can take many forms and generally come from Agere's ASIC libraries. Other offerings allow customers to supply their own core functions for the creation of custom FPSCs. ORCA Foundry Development System The ORCA Foundry development system is used to process a design from a netlist to a configured FPGA. This system is used to map a design onto the ORCA architecture, and then place and route it using ORCA Foundry's timing-driven tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation, and timing analysis. The ORCA Foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow: design entry and the bitstream generation stage. Recent improvements in ORCA Foundry allow the user to provide timing requirement information through logical preferences only; thus, the designer is not required to have physical knowledge of the implementation. FPSC Gate Counting The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count. FPGA/Embedded Core Interface The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of interface signals than on previous FPSC achitectures. Compared to bringing embedded core Agere Systems Inc. 7 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Description (continued) Following design entry, the development system's map, place, and route tools translate the netlist into a routed FPGA. A floorplanner is available for layout feedback and control. A static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation and timing. Timing and simulation output files from ORCA Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPGAs internal configuration RAM, embedded block RAM, and/or FPSC memory. When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined with the front-end tools, ORCA Foundry produces configuration data that implements the various logic and routing options discussed in this data sheet. FPSC Design Kit Development is facilitated by an FPSC design kit which, together with ORCA Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, Synopsys Smart Model (R), and complete online documentation. The kit's software couples with ORCA Foundry, providing a seamless FPSC design environment. More information can be obtained by visiting the ORCA website or contacting a local sales office, both listed on the last page of this document. The architecture consists of four basic elements: programmable logic cells (PLCs), programmable I/O cells (PIOs), embedded block RAMs (EBRs), and systemlevel features. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs are surrounded by common interface blocks which provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. Large blocks of 512 x 18 quadport RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the embedded system bus (ESB). PLC Logic Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional flip-flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-quad fashion; two sets of four LUTs and FFs that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. FPGA Logic Overview The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Agere. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable system-on-chip integration with true plug-and-play design implementation. 8 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver tered or nonregistered. The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os which meet many new communication standards permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed, singleended, and differential-pair signaling (as shown in Table 1). Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output levels. Description (continued) The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3state, bidirectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3state drivers in the SLIC and their direct connections from the PFU outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-world system performance. Programmable I/O The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which allow the user the flexibility to select new I/O types that support high-speed interfaces. Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/flip-flop which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. On the output side of each PIO, an output from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be regis- Routing The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half-chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can be sourced from any I/O pin, PLLs, or the PLC logic. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins. Agere Systems Inc. 9 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 System-Level Features The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block RAMs, universal programmable phase-locked loops, and the addition of highly tuned networking specific phase-locked loops. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed networking systems. Phase-Locked Loops Up to eight PLLs are provided on each Series 4 device, with four PLLs generally provided for FPSCs. Programmable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences. Additional highly tuned and characterized, dedicated phase-locked loops (DPLLs) are included to ease system designs. These DPLLs meet ITU-T G.811 primaryclocking specifications and enable system designers to very tightly target specified clock conditioning not traditionally available in the universal PPLLs. Initial DPLLs are targeted to low-speed networking DS1 and E1, and also high-speed SONET/SDH networking STS-3 and STM-1 systems. These DPLLs are typically not included on FPSC devices and are not found on the ORT8850 family. Microprocessor Interface The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-, 16-, and 32-bit interfaces with optional parity to the Motorola(R) PowerPC 860 bus, it can be used for configuration and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4 embedded system bus at 66 MHz performance. A system-level microprocessor interface to the FPGA user-defined logic following configuration, through the system bus, including access to the embedded block RAM and general user-logic, is provided by the MPI. The MPI supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data FIFOs. Transfer accesses can be single beat (1 x 4-bytes or less), 4beat (4 x 4-bytes), 8-beat (8 x 2-bytes), or 16-beat (16 x 1-bytes). Embedded Block RAM New 512 x 18 quad-port RAM blocks are embedded in the FPGA core to significantly increase the amount of memory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable multiply functions. The user can configure FIFO blocks with flexible depths of 512k, 256k, and 1k including asynchronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can also be preloaded at device configuration time. Agere Systems Inc. System Bus An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA specification Rev 2.0 AHB protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. Master and slave elements are also available for the user-logic and embedded backplane transceiver portion of the 8850. The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset functions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, or from the port clock (for JTAG configuration modes). 10 Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE 1149.2) port is also available meeting insystem programming (ISP) standards (IEEE 1532 Draft). System-Level Features (continued) Configuration The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The configuration data can reside externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for configuring FPGAs. The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface and embedded system bus to perform both programming and readback. Daisy chaining of multiple devices and partial reconfiguration are also permitted. Additional Information Contact your local Agere representative for additional information regarding the ORCA Series 4 FPGA devices, or visit our website at: http://www.agere.com/orca Agere Systems Inc. 11 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 ORT8850 Overview Device Layout The ORT8850 FPSC provides a high-speed backplane transceiver combined with FPGA logic. The device is based on 1.5 V OR4E2 or OR4E6 FPGAs. The OR4E2 has a 26 x 24 array of programmable logic cells (PLCs) and the OR4E6 has a 46 x 44 array. For the ORT8850, several columns of PLCs in these arrays were replaced with the embedded backplane transceiver core. The ORT8850 embedded core comprises a long-haul interface macro and three RapidIO macros for intraboard chip-to-chip or backplane communication. The long-haul interface includes the high-speed interface (HSI) macrocell, the synchronous transport module (STM) macrocell, and a 8B/10B encoder/decoder. The eight full-duplex channels perform data transfer, scrambling/descrambling or encoding/decoding, and framing at the rate of 850 Mbits/s. Each RapidIO block has a transmit and receive section that each contain one LVDS clock buffer pair, one LVDS start-of-cell buffer pair, and eight LVDS clock buffer pairs which are double edge clocked by the corresponding clock. Figure 1 shows the ORT8850 block diagram. links. The HSI macrocell is used for clock/data recovery (CDR) and serialize/deserialize between the 106.25 MHz byte-wide internal data buses and the 850 Mbits/s serial LVDS links. For a 622 Mbits/s SONET stream, the HSI will perform clock and data recovery (CDR) and MUX/deMUX between 77.76 MHz byte-wide internal data buses and 622 Mbits/s serial LVDS links. Each 850 Mbits/s serial link uses a pseudo-SONET protocol. SONET A1/A2 framing is used on the link to detect the 8 kHz frame location. The link is also scrambled using the standard SONET scrambler definition to ensure proper transitions on the link for improved CDR performance. Selectable transport overhead (TOH) bytes are insertable in the transmit direction. All the selectable bytes are inserted from software programmable registers that are accessed via a microprocessor interface. Elastic buffers (FIFOs) are used to align each incoming STS-12 link to the 77.76 MHz clock and 8 kHz frame. These FIFOs will absorb delay variations between the four 622 Mbits/s links due to timing skews between cards and along backplane traces. For greater variations, a streamlined pointer processor (pointer mover) within the STM macro will align the 8 kHz frames regardless of their incoming frame position. The backplane transceiver allows for SONET scrambling and frame alignment or 8-bit/10-bit (8B/10B) encoding/decoding. SONET has the advantage of reduced overhead (3.3% overhead for SONET vs. 25% overhead for 8B/10B). 8B/10B has the advantage of faster synchronization (a few bytes of transferred data for 8B/10B vs. up to 500 s for four frames of data for SONET). The effective data transfer rate for scrambled SONET is greater than 800 Mbits/s while the effective data transfer rate for 8B/10B is greater than 680 Mbits/s. Frame synchronization and multichannel alignment is provided in 8B/10B mode through the use of special K characters. Figure 2 shows the architecture of the ORT8850 backplane transceiver core. Backplane Transceiver Interface The advantage of the ORT8850 FPSC is to bring specific networking functions to an early market presence using programmable logic in a system. The 850 Mbits/s backplane transceiver core allows the ORT8850 to communicate across a backplane or on a given board at an aggregate speed of 6.8 Gbits/s, providing a physical medium for high-speed asynchronous serial data transfer between system devices. This device is intended for, but not limited to, connecting terminal equipment in SONET/SDH, ATM, and IP systems. The backplane transceiver core is used to support a 6.8 Gbits/s interface for backplane connection to a mate TADM042G5 device or other SONET devices such as redundant central crossconnect. The interface is implemented as an eight-channel 850 Mbits/s LVDS 12 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver ORT8850 Overview (continued) 8-bit/10-bit DECODER 850 Mbits/s DATA 8 FULLDUPLEX SERIAL CHANNELS 850 Mbits/s DATA LVDS I/Os CLOCK/DATA RECOVERY BYTEWIDE DATA PSEUDOSONET FRAMER * POINTER MOVER * SCRAMBLING * FIFO ALIGNMENT * SELECTED TOH 8-bit/10-bit ENCODER 311 MHz DDR INTERFACE (RapidIO) ORCA SERIES 4 FPGA LOGIC LVDS I/Os STANDARD FPGA I/Os 311 MHz DDR INTERFACE (RapidIO) LVDS I/Os 311 MHz DDR INTERFACE (RapidIO) LVDS I/Os 1729(F) Figure 1. ORCA ORT8850 Block Diagram Agere Systems Inc. 13 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 ORT8850 Overview (continued) PW R U PR S T FR O M FP G A (G O E S TO ALL BLO C KS ) U P IN TER FA C E S YS TEM BUS IO R IN G RapidIO A YTR IS TN _A U TX TR ISTN _A R STN _U TX_A U TX D _A [31:0] U TX SO C _A W U TXC LK_FPG A PFC LK C S YS EN B_A R STN _R X_A ZR X D _A [31:0] ZR X SO C _A ZR X SO C VIO L_A ZR X ALN VIO L_A W R X C LK _A _FP G A ZR X C LK _A WCD RapidIO B YTR IS TN _B U TX TR ISTN _B R STN _U TX_B U TX D _B [31:0] U TX SO C _B W U TXC LK_FPG A PFC LK C S YS EN B_B R STN _R X_B ZR X D _B [31:0] ZR X SO C _B FP G A ZR X SO C VIO L_B ZR X ALN VIO L_B W R X C LK _B _FP G A ZR X C LK _B WCD 9X 8 8 2 1 4 12X8 8 10 9 1 CDR + STM Y TR ISTN _C U TX TR IS TN _C R STN _U TX_C U TXD _C [31:0] U TX SO C _C W U TXC LK_FPG A PFC LK C S YS EN B _C R STN _R X_C ZR XD _C [31:0] ZR X SO C _C ZR XS O C VIO L_C ZR XA LN VIO L_C W R X C LK _C _FPG A ZR XC LK_C WCD RapidIO C R X C LK _C R EC E IVE M O D U LE R XS O C _C R XD _C [7:0] TR A N SM IT FIFO TX D [31:0] TXS O C TR A N SM IT M O D U LE S O FT C N TL TX S O C _C TXC LK_C R X C LK _B R EC E IVE M O D U LE R XS O C _B R XD _B[7:0] TR A N SM IT FIFO TX D [31:0] TXS O C TR A N SM IT M O D U LE S O FT C N TL TX S O C _B TXC LK_B SO FT C N TL R X C LK _A R EC E IVE M O D U LE R XS O C _A R XD _A[7:0] TR A N SM IT FIFO TX D [31:0] TXS O C TR A N SM IT M O D U LE S O FT C N TL TX S O C _A TXC LK_A TX D _A [7:0] 8 TX D _B [7:0] 8 D A TA + PAR 8B/10B K -C O N TR O L IN P U TS TX LIN E _FP, S YS _FP STM MACRO + CDR S YS _C LK RX (8 CHANNELS) P R O T_SW 8 D A TA + SP E + C 1J1 + PAR +EN 8 R E C O VE R ED C LK S 8 D A TA + TO H _C K_EN + TO H _FP 8 D A TA + TO H _C K_EN TOH BLOCK TO H _C LK 8 8 8 SO FT C N TL 8 TX D _C [7:0] PLL Figure 2. High-Level Diagram of ORT8850 Transceiver 14 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver 8B/10B Encoder/Decoder The ORT8850 facilitates high-speed serial transfer of data in a variety of applications including Gigabit Ethernet, fibre channel, serial backplanes, and proprietary links. The device provides 8B/10B coding/decoding for each channel. The 8B/10B transmission code includes serial encoding/decoding rules, special characters, and error detection. Information to be transmitted over a fibre shall be encoded eight bits at a time into a 10-bit transmission character and then sent serially. The 10-bit transmission characters support all 256 eight-bit combinations. Some of the remaining transmission characters referred to as special characters, are used for functions which are to be distinguishable from the contents of a frame. ORT8850 Overview (continued) HSI Interface The high-speed interconnect (HSI) macrocell is used for clock/data recovery and MUX/deMUX between 106.25 MHz byte-wide internal data buses and 850 Mbits/s external serial links. The HSI interface receives eight 850 Mbits/s serial input data streams from the LVDS inputs and provides eight independent 106.25 MHz byte-wide data streams and recovered clock to the STM macro. There is no requirement for bit alignment since SONET type framing will take place inside the ORT850 core. For transmit, the HSI converts four byte-wide 106.25 MHz data streams to serial streams at 850 Mbits/s at the LVDS outputs. STM Macrocell The STM portion of the embedded core consists of transmitter (Tx) and receiver (Rx) sections. The receiver receives eight byte-wide data streams at 106.25 MHz and the associated clocks from the HSI. In the Rx section, the incoming streams are SONET framed and descrambled before they are written into a FIFO, which absorbs phase and delay variations and allows the shift to the system clock. The TOH is then extracted and sent out on the eight serial ports. The pointer mover consists of three blocks: pointer interpreter, elastic store, and pointer generator. The pointer interpreter finds the synchronous transport signal (STS) synchronous payload envelopes (SPE) and places it into a small elastic store from which the pointer generator will produce eight byte-wide STS-12 streams of data that are aligned to the system timing pulse. In the Tx section, transmitted data for each channel is received through a parallel bus and a serial port from the FPGA circuit. TOH bytes are received from the serial input port and can be optionally inserted from programmable registers or serial inputs to the STS-12 frame via the TOH processor. Each of the eight parallel input buses is synchronized to a free-running system clock. Then the SPE and TOH data is transferred to the HSI. The STM macrocell also has a scrambler/descrambler disable feature, allowing the user to disable the scrambler of the transmitter and the descrambler of the receiver. Also, unused channels can be disabled to reduce power dissipation. FPGA Interface The FPGA logic will receive/transmit frame-aligned (optional for 8B/10B mode) streams of 106.25 MHz data (maximum of eight streams in each direction) from/to the backplane transceiver embedded core. All frames transmitted to the FPGA will be aligned to the FPGA frame pulse which will be provided by the FPGA user's logic to the STM macro. If the receive pointer mover and alignment FIFOs are bypassed, then each channel will provide its own receive clock and receive frame pulse signals. Otherwise, all frames received from the FPGA logic will be aligned to the system frame pulse that will be supplied to the STM macro from the FPGA user's logic. Byte-Wide Parallel Interface Three byte-wide parallel interface are provided on the ORT8850. Each interface provides for transmit and receive of byte-wide data, one control signal, and one clock. Receive data is sampled on both edges of the receive clock and is converted to a 32-bit data bus, which is single-edge clocked by a half-speed clock for transfer to the FPGA logic. Maximum transmit/receive clock rate is 311 MHz and 155 MHz for the internal FPGA clock. This allows for a 622 Mbits/s link data transfer rate. Other functions provided include a check for a minimum number of transferred bytes. The first byte-wide interface (RapidIO A in Figure 2) is always available. The other two interfaces (RapidIO B and RapidIO C) are available when the 850 Mbits/s serial links are not being used. Agere Systems Inc. 15 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 ORT8850 Overview (continued) FPSC Configuration Configuration of the ORT8850 occurs in two stages: FPGA bit stream configuration and embedded core setup. FPGA Configuration Prior to becoming operational, the FPGA goes through a sequence of states, including powerup, initialization, configuration, start-up, and operation. The FPGA logic is configured by standard FPGA bit stream configuration means as discussed in the Series 4 FPGA data sheet. The options for the embedded core are set via registers that are accessed through the FPGA system bus. The system bus can be driven by an external PPC compliant microprocessor via the MPI block or via a user master interface in FPGA logic. A simple IP block, that drives the system by using the user interface and uses very little FPGA logic, is available in the MPI/System Bus application note (AP01-032NCIP). This IP block sets up the embedded core via a state machine and allows the ORT8850 to work in an independent system without an external microprocessor interface. Embedded Core Setup All options for the operation of the core are configured according to the device register map, which is included with the ORT8850 FPSC simulation kit. During the powerup sequence, the ORT8850 device (FPGA programmable circuit and the core) is held in reset. All the LVDS output buffers and other output buffers are held in 3-state. All flip-flops in the core area are in reset state, with the exception of the boundryscan shift registers, which can only be reset by boundary-scan reset. After powerup reset, the FPGA can start configuration. During FPGA configuration, the ORT8850 core will be held in reset and all the local bus interface signals forced high, but the following activehigh signals (PROT_SWITCH_A, PROT_SWITCH_C, TX_TOH_CK_EN, SYS_FP, LINE_FP) will be forced low. The CORE_READY signal sent from the embedded core to FPGA is held low, indicating that the core is not ready to interact with FPGA logic. At the end of the FPGA configuration sequence, the CORE_READY signal will be held low for six SYS_CLK cycles after DONE, TRI_IO and RST_N (core global reset) are high. Then it will go active-high, indicating the embedded core is ready to function and interact with FPGA programmable circuit. During FPGA reconfiguration when DONE and TRI_IO are low, the CORE_READY signal sent from the core to FPGA will be held low again to indicate the embedded core is not ready to interact with FPGA logic. During FPGA partial configuration, CORE_READY stays active. The same FPGA configuration sequence described previously will repeat again. The initialization of the embedded core consists of two steps: register configuration and synchronization of the alignment FIFO. In order to configure the embedded core, the registers need to be unlocked by writing 0x30005 to address 0x30004 and writing 0x80 to address 0x05. Control registers 0x30004 and 0x30005 are lock registers. If the output bus of the data, serial TOH port, and TOH clock and TOH frame pulse are controlled by 3-state registers (the use of the registers for 3-state output control is optional; these output 3state enable signals are brought across the local bus interface and available to the FPGA side), the next step is to activate the 3-state output bus and signals by taking them to functional state from high-impedance state. This can be done by writing 0x01 to correspond bits of the channel registers 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30090, 0x300B0, and 0x300C8. In addition, the synchronization of selected streams is recommended for some networking systems applications. This requires a resync of the alignment FIFO after the enabled channels have a valid frame pulse or 8B/10B control character. See the sections about STM Link Alignment Setup or 8B/10B Link Alignment Setup for more details. 16 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver 8B/10B Mode The ORT8850 facilitates high-speed serial transfer of data in a variety of applications including Gigabit Ethernet, fibre channel, serial backplanes, and proprietary links. In place of the STM interface, the ORT8850 also provides 8B/10B coding/decoding for each channel. The 8B/10B transmission code includes serial encoding/decoding rules, special characters, and error detection. In 8B/10B mode, LSB is received first and transmitted first. The 10-bit encoded transmission characters labeled as a, b, c, d, e, i, f, g, h, and j are transmitted with bit a first and bit j last, where bit a is the LSB and bit j is the MSB. Transmitter Description The data input to the transmitter of each channel is an 8-bit word and a K-control input. The K input is used to identify data or a special character. For each channel, the input data byte is clocked into a FIFO. When K-control is 1, the data on the parallel input is mapped into its corresponding control character. The transmit FIFOs must be initialized upon the deassertion of the RST_N signal. Receiver Description Clock recovery is performed by the HSI on the input data stream for each channel of the ORT8850. The recovered data is then aligned to the 10-bit word boundary. Word alignment is accomplished by detecting and aligning to the 8B/10B comma sequence. The HSI will detect and align to either polarity of the comma sequence. The 10-bit word aligned data is then decoded and the 8-bit output is passed to the alignment FIFOs. Each receive channel provides a FIFO in order to adjust for the skew between the channels and ensure that the first valid data following the comma character is transmitted simultaneously from all the channels that are programmed to be aligned. In the RESET state, each channel is actively searching for the occurence of a comma character. Once the channel is powered up, the comma detect pulse will be found on the doutxx-fp per channel in the FPGA. Receive Channel Sync Block In order to account for skews between the channels, it is necessary to align multiple channels on the comma character boundary. The sync algorithm assumes that either all eight channels, two groups of four channels, or four groups of two channels will be aligned. The ORT8850 powers up in the RESET state in which no channel alignment is done. Generic Backplane Transceiver Application Synchronous Transfer Mode (STM) The combination of ORT8850 and soft IP cores provides a generic data moving solution for non-SONET applications. There is no requirement for SONET knowledge to the users. All that is needed is to supply the pseudo-SONET framer with data, clock, and a 8 kHz frame pulse. The provision registers may also need to be set up, and this can be done through either the FPGA MPI, or in a state machine in the FPGA section (VHDL code available from Agere). The 8 kHz frame pulse must be supplied to the SYS_FP signal. For generic applications, the frame pulse can be created in FPGA logic from the 77.76 MHz SYS_CLK using a simple resettable counter (the frame pulse should only be high for one cycle of the SYS_CLK). A VHDL core that automatically provides the 8 kHz frame pulse is available from Agere. Byte-wide data is then sent to each of the transmit channels as follows: the first 36 bytes transferred will be invalid data (replaced by overhead), where the first byte is sent on the rising edge of SYS_CLK when SYS_FP is high. The next 1044 byte positions can be filled with valid data. This will repeat a total of nine times (36 invalid bytes followed by 1044 valid bytes) at which time the next 8 kHz frame pulse will be found. Thus, 87 out of 90 (96.7%) of the data bytes sent are valid user data. The ORT8850 also supports a transparent mode where only the first 24 bytes are invalid data (A1/A2 frame bytes) followed by 9,684 bytes of valid user data. On the receive side, an 8 kHz pulse must again be supplied to LINE_FP. In this case, however, only the signal DOUT Agere Systems Inc. 17 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Generic Backplane Transceiver Application (continued) TRANSMIT CHANNEL (1 OF 8) PARALLEL DINXX DATAIN FIFO SERIALIZER 8 8B/10B ENCODER 10 TX LVDS ERROR FLAG ALIGNMENT FIFO DOUTXX PARALLEL DATA OUT SYS_CLK COMMA _DET DOUTXX_FP 10b/8b DECODER 10 DESERIALIZER AND BYTE ALIGN DATA CLOCK RECOVERY RX LVDS LCKRX CLOCK RECEIVER CHANNEL (1 OF 8) 1757(F) Figure 3. 8850 with 8B/10B Coding/Decoding Backplane Transceiver Core Detailed Description HSI Macro The 850 high-speed interface (HSI) provides a physical medium for high-speed asynchronous serial data transfer between ASIC devices. The devices can be mounted on the same PC board or mounted on different boards and connected through the shelf backplane. The 850 CDR macro is an eight-channel clockphase select (CPS) and data retime function with serial-to-parallel demultiplexing for the incoming data stream and parallel-to-serial multiplexing for outgoing data. The macrocell can be used as a eight-channel or 16-channel configuration. The ORT8850 uses an eightchannel HSI macro cell. The HSI macro consists of three functionally independent blocks: receiver, transmitter, and PLL synthesizer as shown in Figure 4. The PLL synthesizer block generates the necessary 850 MHz clock for operation from a 212 MHz, 106 MHz, or 85 MHz reference. The PLL synthesizer block is a common asset shared by all eight receive and transmit channels. The PLL reference clock must match the interface frequency. The HSI_RX block receives a differential 850 Mbits/s (or subrates 424 Mbits/s, 212 Mbits/s) serial data without clock at its LVDS receiver input. Based on data transitions, the receiver selects an appropriate 850 MHz clock phase for each channel to retime the data. The retimed data and clock are then passed to the deMUX (deserializer) module. DeMUX module performs serial-to-parallel conversion and provides three possible parallel rates, 212 Mbits/s, 106 Mbits/s, or 85 Mbits/s, where the 106 Mbits/s data is used in SONET mode and the 85 Mbits/s data is used in 8B/10B mode (212 Mbits/s is unused). The HSI_TX block receives 106 Mbits/s (SONET mode), or 85 Mbits/s (8B/10B mode) parallel data at its input. MUX (serializer) module performs a parallel-toserial conversion using an 850 MHz clock provided by the PLL/synthesizer block. The resulting 850 Mbits/s serial data stream is then transmitted through the LVDS driver. The loopback feature built into the HSI macro provides looping of the transmitter data output into the receiver input when desired. All rate examples described here are the maximum rates possible. The actual HSI internal clock rate is determined by the provided reference clock rate. For example, if a 78 MHz reference clock is provided, the HSI macro will operate at 622 Mbits/s. 18 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) RXPWRDN[(n - 1):0] RESETRX (TEST) Rx TSTCLK SERIAL TO PARRALLEL CREG BYPASS CREG LOOPBKEN LOOPBKCH[(n - 1):0] DIN[(n - 1):0] 848 Mbits/s or 424 Mbits/s or 212 Mbits/s DATA CDR CLOCK/DATA ALIGNMENT RETIME SELECT LD[(n - 1):0]RX[9:0] TEN BIT LCKRX[(n - 1):0] WORD ALIGN RC[1:0]CK[(n-1):0] ENCOMMA[(n-1):0] SYSCLK 106 MHz or 85 MHz 848 MHz (850 MHz) SYNTHESIZER PLL COMMADET[(n-1):0] TO ASIC BLOCK 106 MHz or 85 MHz 106 Mbits/s or 85 Mbits/s 1 2 n DEMUX Tx MUX PARRALLEL TO SERIAL LCKPLL 106 Mbits/s or 85 Mbits/s DOUT[(n -1):0] 848 Mbits/s or 424 Mbits/s or 212 Mbits/s DATA BYPASS TSTCLK LD[(n - 1):0] TX[9:0] 106 Mbits/s or 85 Mbits/s 1 2 n MODE CONTROL EN10BIT RESETTX (TEST) 5-8592(F).b Figure 4. HSI Functional Block Diagram Agere Systems Inc. 19 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) STM Transmitter (FPGA Backplane) The synchronous transport module (STM) portion of the embedded core consists of two slices: STM A and B. Each STM slice has four STS-12 transmit channels, which can be treated as a single STS-48 channel. In general, the transmitter circuit receives four byte-wide 77.76 MHz data from the FPGA, which nominally represents four STS-12 streams (A, B, C, and D). This data is synchronized to the system (reference) clock, and an 8 kHz system frame pulse from the FPGA logic. Transport overhead bytes are then optionally inserted into these streams, and the streams are forwarded to the HSI. All byte timing pulses required to isolate individual overhead bytes (e.g., A1, A2, B1, D1--D3, etc.) are generated internally based on the system frame pulse (SYS_FP) received from the FPGA logic. All streams operate byte-wide at 77.76 MHz in all modes. The TOH processor operates from 25 MHz to 77.76 MHz and supports the following TOH signals: A1 and A2 insertion and optional corruption; H1, H2, and H3 pass transparently; BIP-8 parity calculation (after scrambling) and B1 byte insertion and optional corruption (before scrambling); optional K1 and K2 insert; optional S1/M0 insert; optional E1/F1/E2 insert; optional section data communication channel (DCC, D1--D3) and line data communication channel (DCC, D4--D12) insertion (for intercard communications channel); scrambling of outgoing data stream with optional scrambler disabling; and optional stream disabling. All streams operate byte-wide at 77.76 MHz (622 Mbits/s) or 106.25 MHz (850 Mbits/s) in all modes. When the ORT8850 is used in nonnetworking applications as a generic high-speed backplane data mover, the TOH serial ports are unused or can be used for slow-speed, off-channel communication between devices. An optional transparent mode is available where only the twelve A1 and twelve A2 bytes are used for frame alignment and synchronization. Data received on the parallel bus is optionally scrambled and transferred to LVDS outputs. Byte Ordering Information The STM macro slice (i.e., A, B) supports quad STS12, quad STS-3, and quad STS-1 modes of operation on the input/output ports. STS-48 is also supported, but it must be received in the quad STS-12 format. When operating in quad STS-12 mode, each of the independent byte streams carries an entire STS-12 within it. Figure 5 reveals the byte ordering of the individual STS-12 streams and for STS-48 operation. Note that the recovered data will always continue to be in the same order as transmitted. 12 24 36 48 9 21 33 45 6 18 30 42 3 15 27 39 11 23 35 47 8 20 32 44 5 17 29 41 2 14 26 38 10 22 34 46 7 19 31 43 4 16 28 40 1 13 25 37 STS-12 A STS-12 B STS-12 C STS-12 D STS-48 IN QUAD STS-12 FORMAT 1, 12 1, 9 2, 12 2, 9 3, 12 3, 9 4, 12 4, 9 QUAD STS-12 1, 6 2, 6 3, 6 4, 6 1, 3 1, 11 1, 8 2, 3 2, 11 2, 8 3, 3 3, 11 3, 8 4, 3 4, 11 4, 8 1, 5 2, 5 3, 5 4, 5 1, 2 1, 10 1, 7 2, 2 2, 10 2, 7 3, 2 3, 10 3, 7 4, 2 4, 10 4, 7 1, 4 2, 4 3, 4 4, 4 1, 1 2, 1 3, 1 4, 1 STS-12 A STS-12 B STS-12 C STS-12 D 5-8574 (F) Figure 5. Byte Ordering of Input/Output Interface in STS-12 Mode 20 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver In addition to the above hardcoded exceptions, the source of some TOH bytes can be further controlled by software. When configured to be in pass-through mode, the specific bytes must flow transparently from the parallel input. Note that blocks of 12 STS-1 bytes forming an STS-12 are controlled as a whole. There are 15 software controls per channel, as listed below: s Backplane Transceiver Core Detailed Description (continued) Transport Overhead for In-Band Communication The TOH byte can be used for in-band configuration, service, and management since it is carried along the same channel as data. In ORT8850, in-band signaling can be efficiently utilized, since the total cost of overhead is only 3.3%. Transport Overhead Insertion (Serial Link) The TOH serial links are used to insert TOH bytes into the transmit data. The transmit TOH data and TOH_CLK_EN get retimed by TOH_CLK in order to meet setup and hold specifications of the device. The retimed TOH data is shifted into a 288-bit (36-byte by 8-bit) shift register and then multiplexed as an 8-bit bus to be inserted into the byte-wide data stream. Insertion from these serial links or pass-through of TOH from the byte-wide data is under software control. Transport Overhead Byte Ordering (FPGA to Backplane) In the transparent mode, SPE and TOH data received on parallel input bus is transferred, unaltered, to the serial LVDS output. However, B1 byte of STS#1 is always replaced with a new calculated value (the 11 bytes following B1 are replaced with all zeros). Also, A1 and A2 bytes of all STS-1s are always regenerated. TOH serial port in not used in the transparent mode of operation. In the TOH insert mode, SPE bytes are transferred, unaltered, from the input parallel bus to the serial LVDS output. On the other hand, TOH bytes are received from the serial input port and are inserted in the STS12 frame before being sent to the LVDS output. Although all TOH bytes from the 12 STS-1s are transferred into the device from each serial port, not all of them get inserted in the frame. There are three hardcoded exceptions to the TOH byte insertion: s Source of K1 and K2 bytes of the 12 STS-1s (24 bytes) is specified by a control bit (per channel control). Source of S1 and M0 bytes of the 12 STS-1s (24 bytes) is specified by a control bit (per channel control). Source of E1, F1, E2 bytes of the STS-1s (36 bytes) is specified by a control it (per channel control). Source of D1 bytes of the STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D2 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D3 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D4 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D5 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D6 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D7 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D8 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D9 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D10 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D11 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D12 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). s s s s s s s s s s s s s Framing bytes (A1/A2 of all STS-1s) are not inserted from the serial input bus. Instead, they can always be regenerated. Parity byte (B1 of STS#1) is not inserted from the serial input bus. Instead, it is always recalculated (the 11 bytes following B1 are replaced with all zeros). s s TOH reconstruction is dependent on the transmitter mode of operation. In the transparent mode, TOH bytes on LVDS output are as shown in Table 2. A new capability in the ORT8850 allows the user to choose not to insert the B1 byte and the following 11 bytes of zeros. This option is also available for the A1 and A2 bytes. Pointer bytes (H1/H2/H3 of all STS-1s) are not inserted from the serial input bus. Instead, they always flow transparently from parallel input to LVDS output. Agere Systems Inc. s 21 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) Table 2. Transmitter TOH on LVDS Output (Transparent Mode) A1 B1 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 Regenerated bytes. Transparent bytes from parallel input port. In the TOH insert mode of operation, TOH bytes on LVDS output are shown in Table 3. This also shows the order in which data is transferred to the serial TOH interface, starting with the most significant bit of the first A1 byte. The first bit of the first byte is replaced by an even parity check bit over all TOH bytes from the previous TOH frame. Table 3. Transmitter TOH on LVDS Output (TOH Insert Mode) A1 B1 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A1 0 D1 H1 D4 D7 D10 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 A2 E1 D2 H2 K1 D5 D8 D11 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 F1 D3 H3 K2 D6 D9 D12 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 Regenerated bytes. Inserted or transparent bytes. Blocks of 12 STS-1 bytes are controlled as a whole. There are 15 controls/channel: K1/K2, S1/M0, E1/F1/E2, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12. Transparent bytes (from parallel input port). Inserted bytes from TOH serial input port. A1/A2 Frame Insert and Testing The A1 and A2 bytes provide a special framing pattern that indicates where a STS-1 begins in a bit stream. All 12 A1 bytes of each STS-12 are set to 0xF6, and all 12 A2 bytes of the STS-12 are set to 0x28 when not overridden with an user-specified value for testing. The latency from the transmission of the first bit of the A1 byte at the device output pins from the transmit frame pulse (SYS_FP) at the FPGA to embedded core input is between five to seven cycles of fpga_sysclk. A1/A2 testing (corruption) is controlled per stream by the A1/A2 error insert register. When A1/A2 corruption detection is set for a particular stream, the A1/A2 values in the corrupted A1/A2 value registers are sent for the number of frames defined in the corrupted A1/A2 frame count register. When the corrupted A1/A2 frame count register is set to zero, A1/A2 corruption will continue until the A1/A2 error insert register is cleared. This also allows alternate values to be set for A1 and A2 during normal operation. For the ORT8850, it is optionally possible to not insert A1 and A2. On a per-device basis, the A1 and A2 byte values are set, as well as the number of frames of corruption. Then, to insert the specified A1/A2 values, each channel has an enable register. When the enable register is set, the A1/A2 values are corrupted for the number specified in the number of frames to corrupt. To insert errors again, the perchannel fault insert register must be cleared, and set again. Only the last A1 and the first A2 are corrupted. 22 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver FPGA to the STM will be aligned to the frame pulse SYS_FP that is supplied to the STM macro. In either direction, the system frame pulse and line frame pulse are active for one system clock cycle, indicating the location of A1 byte of STS#1. They are common to all eight channels except when the pointer mover and alignment FIFOs are bypassed. In that case, a line frame pulse for each receive channel is generated by the STM macro and passed to the FPGA interface. Repeater This block is essentially the inverse of the sampler block. It receives byte-wide STS-12 rate data from the TOH insert block. In order to support the quad STS-1 and STS-3 modes of operation, the HSI (622 Mbits/s) can be connected to a slower speed device (e.g., 155 Mbits/s or 52 Mbits/s). The purpose of this block is to rearrange the data being fed to the HSI so that each bit is transmitted four or twelve times, thus simulating 155 Mbits/s or 51.84 Mbits/s serial data. For example, in STS-3 mode, the incoming STS-12 stream is composed of four identical STS-3s so only every fourth byte is used. The bit expansion process takes a single byte and stretches it to take up 4 bytes each consisting of 4 copies of the 8 bits from the original byte. In STS-1 mode, every twelfth byte is used and four groups of 3 bytes of the form AAAAAAAA, AAAABBBB, and BBBBBBBB are forwarded to the HSI. An alternate method for supplying STS-1 mode is to set the HSI to run at 207.36 MHz and use the four times repeater function. Backplane Transceiver Core Detailed Description (continued) B1 Calculation and Insertion In a bit interleaved parity -8 (BIP-8) error check set for even parity over all the bits of an STS-1 frame B1 is defined for the first STS-1 in an STS-N only, the B1 calculation block computes a BIP-8 code, using even parity over all bits of the previous STS-12 frame after scrambling and is inserted in the B1 byte of the current STS-12 frame before scrambling. Per-bit B1 corruption is controlled by the force BIP-8 corruption register (register address 0F). For any bit set in this register, the corresponding bit in the calculated BIP-8 is inverted before insertion into the B1 byte position. Each stream has an independent fault insert register that enables the inversion of the B1 bytes. B1 bytes in all other STS1s in the stream are filled with zeros. For the ORT8850, it is optionally possible to not insert B1 and the subsequent 11 bytes of zeros. Stream Disable When disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all ones, feeding the HSI. The HSI macro is powered down on a per-stream basis, as are its LVDS outputs. Scrambler The data stream is scrambled using a frame-synchronous scrambler with a sequence length of 127. The scrambling function can be disabled by software. The generating polynomial for the scrambler is 1 + x6 + x7. This polynomial conforms to the standard SONET STS-12 data format. The scrambler is reset to 1111111 on the first byte of the SPE (byte following the Z0 byte in the twelfth STS-1). That byte and all subsequent bytes to be scrambled are exclusive-ORed, with the output from the byte-wise scrambler. The scrambler runs continuously from that byte on throughout the remainder of the frame. A1, A2, J0, and Z0 bytes are not scrambled. System Frame Pulse and Line Frame Pulse System frame pulse (for transmitter) and line frame pulse (for receiver) are generated in FPGA logic. A1/A2 framing is used on the link for locating the 8 kHz frame location. All frames sent to the FPGA are aligned to the FPGA frame pulse LINE_FP which is provided by the FPGA to the STM macro. All frames sent from the STM Receiver (Backplane FPGA) Each of the two STM slices of the ORT8850 has four receiving channels that can be treated as one STS-48 stream, or treated as independent channels. Incoming data is received through LVDS serial ports at the data rate of 622 Mbits/s. The receiver can handle the data streams with frame offsets of up to 12 bytes which would be due to timing skews between cards and along backplane traces or other transmission medium. In order for this multichannel alignment capability to operate properly, it should be noted that while the skew between channels can be very large, they must operate at the exact same frequency (0 ppm frequency deviation), thus requiring that their transmitters be driven by the same clock source. The received data streams are processed in the HSI and the STM, and then passed through the CIC boundary to the FPGA logic. Agere Systems Inc. 23 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) Framer Block The framer block takes byte-wide data from the HSI, and outputs a byte-aligned, byte-wide data stream and 8 kHz sync pulse. The framer algorithm determines the out-of-frame/in-frame status of the incoming data and will cause interrupts on both an errored frame and an out-of-frame (OOF) state. The framer detects the A1/ A2 framing pattern and generates the 8 kHz frame pulse. When the framer detects OOF, it will generate an interrupt. Also, the framer detects an errored frame and increments an A1/A2 frame error counter. The counter can be monitored by a processor to compile performance status on the quality of the backplane. Because the ORT8850 is intended for use between it and another ORT8850 or other devices via a backplane, there is only one errored frame state. Thus, after two transitions are missed, the state machine goes into the OOF state and there is no severely errored frame (SEF) or loss-of-frame (LOF) indication. B1 Calculate Each Rx block receives byte-wide scrambled 77.76 MHz data and a frame sync from the framer. Since each HSI is independently clocked, the Rx block operates on individual streams. Timing signals required to locate overhead bytes to be extracted are generated internally based on the frame sync. The Rx block produces byte-wide (optionally) descrambled data and an output frame sync for the alignment FIFO block. The frame sync signals are also sent to the FPGA logic for use when the alignment FIFO block is bypassed. The B1 calculation block computes a BIP-8 (bit interleaved parity 8 bits) code, using even parity over all bits of the previous STS-12 frame before descrambling; this value is checked against the B1 byte of the current frame after descrambling. A per-stream B1 error counter is incremented for each bit that is in error. The error counter may be read via the CPU interface. Descrambling. The streams are descrambled using a frame synchronous descrambler with a sequence length of 127 with a generating polynomial of 1 + x6 + x7. The A1/A2 framing bytes, the section trace byte (J0) and the growth bytes (Z0) are not descrambled. The descrambling function can be disabled by software. Sampler. This block operates on the byte-wide data directly from the HSI macro. The HSI external interface always runs at 622 Mbits/s (STS-12), or 850 Mbits/s, but it can be connected directly to a 155 Mbits/s STS-3 stream or a 51.84 Mbits/s STS-1 stream. If connected to either a 155 Mbits/s or 51.84 Mbits/s stream, each incoming data is received either 4 or 12 times respectively. This block is used to return the byte stream to the expected STS-12 format. The mode of operation is controlled by a register and can either be STS-12 (pass-through), STS-3 (every fourth bit), or STS-1 (every twelfth bit). The output from this block is not bitaligned (i.e., an 8-bit sample does not necessarily contain an entire SONET byte), but it is in standard SONET STS-12 format (i.e., four STS-3s or 12 STS1s) and is suitable for framing. AIS-L Insertion. Alarm indication signal (AIS) is a continuous stream of unframed 1s sent to alert downstream equipment that the near-end terminal has failed, lost its signal source, or has been temporarily taken out of service. If enabled in the AIS_L force register, AIS-L is inserted into the received frame by writing all ones for all bytes of the descrambled stream. AIS-L Insertion on Out-of-Frame. If enabled via a register, AIS-L is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out-of-frame condition exists. Internal Parity Generation Even parity is generated on all data bytes and is routed in parallel with the data to be checked before the protection switch MUX at the parallel output. 24 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) Transport Overhead Extraction Transport overhead is extracted from the receive data stream by the TOH extract block. The incoming data gets loaded into a 36-byte shift register on the system clock domain. This, in turn, is clocked onto the TOH clock domain at the start of the SPE time, where it can be clocked out. During the SPE time, the receiver TOH frame pulse is generated, RX_TOH_FP, which indicates the start of the row of 36 TOH bytes. This pulse, along with the receive TOH clock enable, RX_TOH_CK_EN, as well as the TOH data, are all launched on the rising edge of the TOH clock TOH_CLK. TOH Byte Ordering The TOH processor is responsible for dropping all TOH bytes of each channel through one of four corresponding serial ports. The four TOH serial ports are synchronized to the TOH clock (the same clock that is being used by the serial ports on the transmitter side). This free-running TOH clock is provided to the core by external circuitry and operates at a minimum frequency of 25 MHz and a maximum frequency of 77.76 MHz. Data is transferred over serial links in a bursty fashion as controlled by the Rx TOH clock enable signal, which is generated by the ASIC and common to the four channels. All TOH bytes of STS-12 streams are transferred over the appropriate serial link in the same order in which they appear in a standard STS-12 frame. Data transfer should be preformed on a rowby-row basis such that internal data buffering needs is kept to a minimum. Data transfers on the serial links will be synchronized relative to the Rx TOH frame signal. Receiver TOH Reconstruction Receiver TOH reconstruction on output parallel bus is as shown in the following table (if the pointer mover is not bypassed). Table 4. Receiver TOH (Output Parallel Bus) A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A2 0 0 H2 K1 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 0 0 0 H3 K2 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 0 0 0 H3 0 0 0 0 0 Regenerated bytes. Regenerated bytes (under pointer generator control, SS bits must be transparent, AIS-P must be supported). Bytes taken from elastic store buffer, on negative stuff opportunity-else, forced to all zeros. Transparent or all zeros (K1/K2 are either taken from K1/K2 buffer or forced to all zeros-soft, control). In transparent mode, AIS-L must be supported. All zero bytes. On the TOH serial port, all TOH bytes are dropped as received on the LVDS input (MSB first). The only exception is the most significant bit of byte A1 of STS#1, which is replaced with an even parity bit. This parity bit is calculated over the previous TOH frame. Also, on AIS-L (either resulting from LOF or forced through software), all TOH bits are forced to all ones with proper parity (parity automatically ends up being set to 1 on AIS-L). Special TOH Byte Functions K1 and K2 Handling. The K1 and K2 bytes are used in automatic protection switch (APS) applications. K1 and K2 bytes can be optionally passed through the pointer mover under software control, or can be set to zero with the other TOH bytes. A1 and A2 Handling. As discussed previously, the A1 and A2 bytes are used for a framing header. A1 and A2 bytes are always regenerated and set to hexadecimal F6 and 28, respectively. Agere Systems Inc. 25 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) SPE and C1J1 Outputs. These two signals for each channel are passed to the FPGA logic to allow a pointer processor or other function to extract payload without interpreting the pointers. For the ORT8850, each frame has 12 STS-1s. In the SPE region, there are 12 J1 pulses for each STS-1s. There is one C1(J0, new SONET specifications use J0 instead of C1 as section trace to identify each STS-1 in an STS-N) pulse in the TOH area for one frame. Thus, there is a total of 12 J1 pulses and one C1(J0) pulse per frame. C1(J0) pulse is coincident with the J0 of STS1 #1. In each frame, the SPE flag is active when the data stream is in SPE area. SPE behavior is dependent on pointer movement and concatenation. Note that in the TOH area, H3 can also carry valid data. When valid SPE data is carried in this H3 slot, SPE is high in this particular TOH time slot. In the SPE region, if there is no valid data during any SPE column, the SPE signal will be set to low. SPE allows a pointer processor to extract payload without interpreting the pointers. The SPE and C1J1 functionality are described in Table 5. For generic data operation, valid data is available when SPE is 1 and the C1J1 signal is ignored. Table 5. SPE and C1J1 Functionality SPE 0 0 C1J1 0 1 Description TOH information excluding C1(J0) of STS1 #1. Position of C1(J0) of STS1 #1 (one per frame). Typically used to provide a unique link identification (256 possible unique links) to help ensure cards are connected into the backplane correctly or cables are connected correctly. SPE information excluding the 12 J1 bytes. Position of the 12 J1 bytes. 1 1 0 1 Note:The following rules are observed for generating SPE and C1J1 signals: on occurrence of AIS-P on any of the STS-1, there is no corresponding J1 pulse. In case of concatenated payloads (up to STS48c), only the head STS-1 of the group has an associated J1 pulse. C1J1 signal tracks any pointer movements. During a negative justification event, SPE is set high during the H3 byte to indicate that payload data is available. During a positive justification event, SPE is set low during the positive stuff opportunity byte to indicate that payload data is not available. STS-12 TOH ROW # 1 SPE ROW # 1 first SPE BYTES OF THE 12 STS-1S A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 1 2 3 4 5 6 7 8 9 10 11 12 STS-12 SPE C1 PULSE C1J1 J1 PULSE OF 3RD STS-1 5-9330(F) Note: C1J1 signal behavior shown in this figure is just for illustration purposes: C1 pulse position must always be as shown; however, position of J1 pulses vary based on path overhead location of each STS-1 within the STS-12 stream. C1J1 signal must always be active during C1(J0) time slot of STS#1. C1J1 signal must also be active during the twelve J1 time slots. However, C1J1 must not be active for any STS-1 for which AIS-P is generated. Also, on concatenated payloads, only the head of the group must have a J1 pulse. Figure 6. SPE and C1J1 Functionality 26 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) STS-12 TOH ROW # 4 SPE ROW # 4 NEGATIVE STUFF OPPORTUNITY BYTES POSITIVE STUFF OPPORTUNITY BYTES H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 1 2 3 4 5 6 7 8 9 10 11 12 STS-12 SPE SIGNAL SHOWS NEGATIVE STUFFING FOR 2ND STS-1, AND POSITIVE STUFFING FOR 6TH STS-1 SPE 5-9331 Note: SPE signal behavior shown in this figure is just for illustration purposes: SPE behavior is dependent on pointer movements and concatenation. SPE signal must be high during negative stuff opportunity byte time slots (H3) for which valid data is carried (negative stuffing). SPE signal must be low during positive stuff opportunity byte time slots for which there is no valid data (positive stuffing). Figure 7. SPE Stuff Bytes STM FIFO Alignment (Backplane FPGA) The alignment FIFO allows the transfer of all data to the system clock. The FIFO sync block (Figure 8) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures that matching STS-12 streams will arrive at the FPGA end in perfect data sync. The frame alignment is configurable to allow for the possibility of fully independent (i.e., total frame misalignment) STS-12s. Agere Systems Inc. 27 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) all four streams in STM A are in the correct mode when synchronization takes place, then those streams may be enabled or disabled without affecting synchronization. These streams can be frame-aligned in the patterns shown in Figure 10, Figure 9, and Figure 11. ALL 8 ALIG N M E NT O F STM A A ND STM B STM A Stream A STM A Stream B STM A Stream A STM A Stream B S TM A S tream C S TM A S tream D STM B Stream A STM B Stream B S TM B S tream C S TM B S tream D STS-12 STREAM AA STS-12 STREAM AB STS-12 STREAM AC STS-12 STREAM AD FIFO SYNC STS-12 STREAM BA STS-12 STREAM BB STS-12 STREAM BC STS-12 STREAM BD STM SLICE A S TM A S tream C S TM A S tream D STM B Stream A STM B Stream B S TM B S tream C S TM B S tream D t0 0674 Figure 9. Example of Inter-STM Alignment STM SLICE B ALL 4 ALIG N M E NT O F STM A A ND STM B STM A Stream A STM A Stream B S TM A S tream C S TM A S tream D STM A Stream A STM A Stream B S TM A S tream C S TM A S tream D STM B Stream A STM B Stream B STM B Stream C STM B Stream D 5-8577 (F) STM B Stream A STM B Stream B S TM B S tream C S TM B S tream D Figure 8. Interconnect of Streams for FIFO Alignment The incoming data from the HSI (also referred to as CDRM850) can be separated into four STS-12 channels (A, B, C, and D) per slice. Thus, there are STS-12 channels AA to AD from slice A of the STM and STS12 channels BA to BD of slice B. These streams can be frame-aligned in the following patterns: in STS-48 mode, all four STS-12s of each STM slice are aligned with each other (i.e., AA, AB, AC, AD). Optionally, in STS-48 mode, all eight STS-12s (STMs A and B) can be aligned (to allow hitless switching at the STS-48 level). Multiple devices can be aligned to enable STS192 or higher modes. Streams can also be aligned on a twin STS-12 basis. There is also a provision to allow certain streams to be disabled (i.e., not producing interrupts or affecting synchronization). These streams can be enabled at a later time without disrupting other streams. If the selected stream needs to be a part of a bigger group (i.e., STM A), then either the entire group must be resynched or the affected stream must have been in the correct mode (i.e., align all STM A) when the initial synchronization was performed. As long as 28 t1 t0 0673(F) Figure 10. Example of Intra-STM Alignment TWINS ALIGNMENT OF STREAMS A AND C S TM A Stream A STM B Stream A STM A Stream B STM B Stream B STM A Stream C S TM B Stream C STM A S tream D S TM B Stream D STM A S tream A STM B Stream A STM A Stream B STM B S tream B S TM A Stream C STM B Stream C S TM A Stream D STM B S tream D t0 t1 0675 Figure 11. Example of Twin STS-12 Stream Alignment Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver address for the FIFO block. The first A1 in every STS12 stream is written in the same location (address 0) in the FIFO. Also, a frame bit is passed through the FIFO along with the first byte before the first A1 of the STS12. The read control block synchronizes the reading of the FIFO for streams that are to be aligned. Reading begins when the FIFO sync signals that all of the applicable A1s and the appropriate margin have been written to the FIFO. All of the read blocks to be synchronized begin reading at the same time and same location in memory (address 0). The alignment algorithm takes the difference between read address and write address to indicate the relative clock alignments between STS-12 streams. If this depth indication exceeds certain limits (12 clocks), then an interrupt is given to the microprocessor (alignment overflow). Each STS-12 stream can be realigned by software if it gets too far out of line (this would cause a loss of data). For background applications that have less than 154.3 ns of interlink skew, misalignment will not occur. STM Link Alignment Setup In order to ensure proper operation of the STM Link Alignment capability, the following setup procedures should be followed after the enabled channels have a valid frame pulse: 1. Put all of the streams to be aligned, including disabled streams, into their required alignment mode. 2. Force AIS-L in all streams to be synchronized (refer to register map, write 0x01 to DB6 or register 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30098, 0x300B0, and 0x300C8). 3. Wait four frames. Write a 0x01 to the FIFO alignment resync register bits as required in register 0x30017 or 0x30018. Wait four frames. 4. Release the AIS-L in all streams (write 0x00 to DB6 or register 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30098, 0x300B0, and 0x300C8). This procedure allows normal data flow through the embedded core. Backplane Transceiver Core Detailed Description (continued) The FIFO block consists of a 24-bit by 10-bit FIFO per link. This FIFO is used to align up to 154.3 ns of interlink skew and to transfer to the system clock. The FIFO sync circuit takes metastable hardened frame pulses from the write control blocks and produces sync signals that indicate when the read control blocks should begin reading from the first FIFO location. On top of the sync signals, this block produces an error indicator which indicates that the signals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). Sync and error signals are sent to read control block for alignment. The read control block is synched only once on start-up; any further synchronization is software controlled. The action of resynching a read control block will always cause loss of data. A register allows the read control block to be resynched. STM Link Alignment The general operation of the link alignment algorithm is to wait 12 clocks (i.e., half the FIFO) from the arriving frame pulse and then signal the read control block to begin reading. For perfectly aligned frame pulses across the links, it is simply a matter of counting down 12 and then signaling the read control block. The algorithm down counts by one until all of the frame pulses have arrived and then by two when they are all present. For example (Figure 12), if all pulses arrive together, then alignment algorithm would count 24 (12 clocks); if, however, the arriving pulses are spread out over four clocks, then it would count one for the first four pulses and then two per clock afterward, which gives a total of 14 clocks between first frame pulse and the first read. This puts the center of arriving frame pulses at the halfway point in the buffer. This is the extent of the algorithm, and it has no facility for actively correcting problems once they occur. The write control block receives byte-wide data at 77.76 MHz and a frame pulse two clocks before the first A1 byte of the STS-12 frame. It generates the write 12 C LO C K S 10 C LO C K S LA S T FP A R R IV E S A LL FP s A R R IV E TO G E TH E R (W R ITIN G B E G IN S ) 24-byte FIFO S Y N C . P U LS E (R E A D IN G B E G IN S ) 4 C LO C K S FIR S T FP A R R IV E S (W R ITIN G B E G IN S ) 24-byte FIFO S Y N C P U LS E (R E A D IN G B E G IN S ) P E R FE C TLY A LIG N E D FR A M E S 4-B Y TE S P R E A D IN A R R IV IN G FR A M E S 5-8584 (F) Figure 12. Examples of Link Alignment Agere Systems Inc. 29 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) 8B/10B Transmitter (FPGA Backplane) For each channel, an 8B/10B encoder can be enabled in place of the STM transmitter. This block receives 8-bit data from the FPGA interface, encodes it into a 10-bit code, and then sends this 10-bit code to the HSI block for serialization and transmission from the ORT8850. This 8-bit to 10-bit encoding provides for guaranteed transmission of a large number of transmissions to allow for easy recovery by a CDR on the other end of the backplane or transmission medium, and also allows for the insertion of control characters. These control characters have many uses, including their use in the ORT8850 to align 10-bit word boundries and perform multi-channel alignments, as will be discussed in the 8B/10B receiver section. The data input to the transmitter of each channel from the FPGA logic is an 8-bit word and K-control input. The Kcontrol input is used to designate data or a special character, where a logic 1 indicates that the data should be mapped to a control character. The following table shows this mapping that is supported. Two different codings are possible for each data value and are shown as encoded word (+) and encoded word (-). The transmitter selects between the positive or negative encoded word based on the calculated disparity of the present data. Table 6. Valid Special Characters K character K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 K28.6 K28.7 K23.7 K27.7 K29.7 K30.7 HGF EDCBA 765 43210 000 11100 001 11100 010 11100 011 11100 100 11100 101 11100 110 11100 111 11100 111 10111 111 11011 111 11101 111 11110 K control 1 1 1 1 1 1 1 1 1 1 1 1 Encoded Word (-) abcdei fghj 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000 Encoded Word (+) abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111 It should also be noted that the data is serialized in the reverse order from the STM block, where dinxy[0] is transmitted first (the 8B/10B receive block also deserializes in the reverse order of the STM receive block). 8B/10B Receiver (Backplane FPGA) Instead of using the STM receiver block in the ORT8850, a separate decoder block is available to allow for receiving data that has been encoded using a standard 8B/10B encoder. This encoding/decoding scheme also allows for the transmission of special characters and allows for error detection. Clock recover for the 8B/10B decoder is performed by the HSI block for each of the eight receive channels in the ORT8850. This recovered data is then aligned to a 10-bit word boundry by detecting and aligning to the commacodeword. Word alignment is done to either polarity of this codeword. The 10-bit code word is passed to the decoder, which provides an 8-bit byte of data and a COMMADET signal to the multi-channel alignment block. In 8B/10B mode, the receiver can handle 12 bytes of skew between channels which would be due to timing skews between cards and along backplane trace or other transmission medium. In order for this multi-channel alignment capability to operate properly, it should be noted that while the skew between channels can be very large, they must operate at the exact same frequency (0 ppm frequency deviation), thus requiring their transmitters to be driven by the same clock source. This alignment FIFO can be bypassed. The COMMADET signal is also provided to the FPGA logic per channel on the signal doutxy_fp, where x designates either four-channel macro A or B, while y designates the channel (A, B, C, D) in each macro. 30 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) 8B/10B Link Alignment Setup In order to align the receive channels in 8B/10B mode, the following procedure should be followed: 1. Enable 8B/10B mode for all eight channels by setting the EN10BIT found at control register address 0xe0 (bit # 1). 2. Enable the ENCOMMA bits for all used channels at control register address 0x300e3 (one bit per channel). 3. Put all of the streams to be aligned, including disabled streams, into their required alignment mode. 4. Transmit at least 100 packets across each link to be aligned. 5. Write a 0x01 to the FIFO alignment resync register bits as required in control register 0x30017 or 0x30018. Pointer Mover Block (Backplane FPGA) The pointer mover maps incoming frames to the line framing that is supplied by the FPGA logic. There is a separate pointer mover for the two STM macro slices, A and B, each of which handles up to one STS-48 (four channels), but there is only one line frame pulse imput (line_fp) shared by both pointer mover blocks. The K1/K2 bytes and H1-SS bits are also passed through to the pointer generator so that the FPGA can receive them. The pointer mover handles both concatenations inside the STS-12, and to other STS-12s inside the core. The pointer mover block can correctly process any length of concatenation of STS frames (multiple of three) as long as it begins on an STS-3 boundary (i.e., STS-1 number one, four, seven, ten, etc.) and is contained within the smaller of STS-3, 12, or 48. See details in Table 7. Table 7. Valid Starting Positions for an STS-Mc STS-1 Number 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 STS-3cSPE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes STS-6cSPE Yes Yes Yes No Yes Yes Yes No Yes Yes Yes No Yes Yes Yes No STS-9cSPE Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes No No STS-12cSPE Yes No No No Yes No No No Yes No No No Yes No No No STS-15cSPE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No STS-18c to STS-48c SPEs Yes -- -- -- -- -- -- -- -- -- -- No No No No No Note: Yes = STS-Mc SPE can start in that STS-1. No = STS-Mc SPE cannot start in that STS-1. -- = Yes or no, depending on the particular value of M. Agere Systems Inc. 31 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) NORM Pointer Interpreter State Machine. The pointer interpreter's highest priority is to maintain accurate data flow (i.e., valid SPE only) into the elastic store. This will ensure that any errors in the pointer value will be corrected by a standard, fully SONET compliant, pointer interpreter without any data hits. This means that error checking for increment, decrement, and new data flag (NDF) (i.e., 8 of 10) is maintained in order to ensure accurate data flow. A single valid pointer (i.e., 0--782) that differs from the current pointer will be ignored. Two consecutive incoming valid pointers that differ from the current pointer will cause a reset of the J1 location to the latest pointer value (the generator will then produce an NDF). This block is designed to handle single bit errors without affecting data flow or changing state. The pointer interpreter has only three states (NORM, AIS, and CONC). NORM state will begin whenever two consecutive NORM pointers are received. If two consecutive NORM pointers that both differ from the current offset are received, then the current offset will be reset to the last received NORM pointer. When the pointer interpreter changes its offset, it causes the pointer generator to receive a J1 value in a new position. When the pointer generator gets an unexpected J1, it resets its offset value to the new location and declares an NDF. The interpreter is only looking for two consecutive pointers that are different from the current value. These two consecutive NORM pointers do not have to have the same value. For example, if the current pointer is ten and a NORM pointer with offset of 15 and a second NORM pointer with offset of 25 are received, then the interpreter will change the current pointer to 25. The receipt of two consecutive CONC pointers causes CONC state to be entered. Once in this state, offset values from the head of the concatenation chain are used to determine the location of the STS SPE for each STS in the chain. Two consecutive AIS pointers cause the AIS state to occur. Any two consecutive normal or concatenation pointers will end this AIS state. This state will cause the data leaving the pointer generator to be overwritten with 0xFF. 2 C xN ON M OR xC M 2 OR xA 2 xN IS 2 2 x CONC CONC 2 x AIS 5-8589 (F) AIS Figure 13. Pointer Mover State Machine Pointer Generator. The pointer generator maps the corresponding bytes into their appropriate location in the outgoing byte stream. The generator also creates offset pointers based on the location of the J1 byte as indicated by the pointer interpreter. The generator will signal NDFs when the interpreter signals that it is coming out of AIS state. The pointer generator resets the pointer value and generates NDF every time a byte marked J1 is read from the elastic store that doesn't match the previous offset. Increment and decrement signals from the pointer interpreter are latched once per frame on either the F1 or E2 byte times (depending on collisions); this ensures constant values during the H1 through H3 times. The choice of which byte time to do the latching on is made once when the relative frame phases (i.e., received and system) are determined. This latch point is then stable unless the relative framing changes and the received H byte times collide with the system F1 or E2 times, in which case the latch point would be switched to the collision-free byte time. There is no restriction on how many or how often increments and decrements are processed. Any received increment or decrement is immediately passed to the generator for implementation regardless of when the last pointer adjustment was made. The responsibility for meeting the SONET criteria for maximum frequency of pointer adjustments is left to an upstream pointer processor. When the interpreter signals an AIS state, the generator will immediately begin sending out 0xFF in place of data and H1, H2, H3. This will continue until the interpreter returns to NORM or CONC (pointer mover state machine) states and a J1 byte is received. 32 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver STM Redundancy and Protection Switching The ORT8850 supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. For the transmitter mode, no additional functionality is required for redundant operation. For receiving data, STS-12 and STS-48 data redundancy can be implemented within the same device, while STS-192 and above data stream requires multiple ORT8850 devices to support redundancy. In STS-12 mode, the channel A receive data bus port is used for both channel A and channel B. Similarly, the channel C receive data bus port is used for both channel C and channel D. Channel B and channel D become the redundant channels. The channel B and channel D receive data bus ports are unused. Soft registers provide independent control to the protection switching MUXes for both parallel data ports and serial TOH data ports. When direct hardware control for protection switching is needed, external protection switch pins are available for channels A and B, and also channels C and D. The external protection switch pins only support parallel SPE/TOH data protection switching, but not the serial TOH data. these protection switching pins are listed in Table 28 as prot_switch_xx. For STS-48 redundancy, the two 4-channel macro blocks are both used: four channels for work and four channels for protect. The switching between work and protect is extended to either be between four-channel macros or between the A/B and C/D channels within both macros. In STS-192 mode, multiple independent devices are required to work and protect for redundancy. Parallel and serial port output pins on the FPGA side should be 3-stated as the basis for supporting redundancy. The existing local bus enable signals at the CIC can be used as 3-state controls for FPGA data bus if needed, which can be easily accessed by software control. Users can also create their own protection switch 3-state enable signals either in FPGA logic or external to the device, depending on the specific application. The STM protection switch circuitry is not available in 8B/10B mode or STM pointer mover and alignment FIFO bypass mode. It is available when only the pointer mover is bypassed. Backplane Transceiver Core Detailed Description (continued) Receive Bypass Options and FPGA Interface Not all of the blocks in the receive direction are required to be used. The following bypass options are valid in the receive (backplane FPGA) direction: s STM Pointer Mover bypass: -- In this mode, data from the alignment FIFOs is transferred to the FPGA logic. All channels are synchronous to the fpga_sysclk signals driven to the FPGA logic, as is also the case when the pointer mover is not bypassed. During bypass SPE, C1J1, and data parity signals are not valid. When the pointer mover is bypassed, a frame pulse from aligned channels (doutxy_fp) is provided by the embedded core. When the pointer mover is used, the FPGA logic provides the frame pulse on the line_fp signal. STM Pointer Mover and Alignment FIFO bypass: -- In this mode, data from the framer block is transferred to the FPGA logic. All channels supply data and frame pulses synchronous with their individual recovered clock (cdr_clk_xy) per channel. During bypass, SPE, C1J1, and data parity signals are not valid. 8B/10B Alignment FIFO bypass: -- When in 8B/10B mode, the data from the 8B/10B decoder is passed to the FPGA logic if the alignment FIFO is bypassed. All channels suppply data and COMMADET signals synchronous with their individual recovered clock (cdr_clk_xy) per channel. When not bypassed, the 8B/10B alignment clock provides all channels and a COMMADET signal synchronous to the fpga_sysclk signal to the FPGA logic. s s Powerdown Mode Powerdown mode will be entered when the corresponding channel is disabled. Channels can be independently enabled or disabled under software control. Parallel data bus output enable and TOH serial data output enable signals are made available to the FPGA logic. The HSI macrocell's corresponding channel is also powered down. The device will power up with all eight channels in powerdown mode. Agere Systems Inc. 33 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) LVDS Protection Switching Each SERDES link sends and receives data on two LVDS buffers. For example, data is transmitted through SERDES AA to tx_b[0] as the work link and tx_c[0] as the protect link. Data is received through two LVDS buffers and a switch is provided to select between the work and protect buffer. The signal lvds_prot_aa provided in the FPGA logic selects between the work link buffer (rx_b[0]) and the protect link buffer (rx_c[0]). These signals select the protect link when high and the work link when low. LVDS protection switching can be used in either 8B/ 10B mode or when using STM. STM redundancy and protection switching discussed in the previous section can only be used with the STM. LVDS protection switching can also be switched using software control. Consult the memory map in Table 10 for more information. FPGA logic array. For example, byte-wide 311 MHz DDR data is converted to 155 MHz 32-bit wide data at the FPGA interface. The primary task of the RapidIO is to process bytes of data known as octets transmitted as a group known as a cell. An octet is described as 8 bits found within a cell. Once the first octet of a cell is received, subsequent octets are part of an uninterrupted data stream until the entire cell has been received. The beginning of the next cell will determine the boundary of the previous cell. The beginning of a cell is indicated by a pulse on the start-of-cell, SOC signal. The SOC signal always accompanies the cell data. At the I/O boundary, cell data is present on an 8-bit data bus with the first octet and SOC aligned with the rising edge of the clock. At the FPGA end, cell data is present on a 32-bit data bus. Thus, the RapidIO is used to translate between the 32-bit data bus and the 8-bit I/O data bus while monitoring the integrity of the cells being processed. Receive Cell Interface The receive interface performs demultiplexing from four sequential octets of eight pairs of LVDS pins using both edges of the high-speed clock onto internal 32-bit buses at the low-speed clock. The interface includes the following signals (see Figure 14): s RapidIO Interface to Pi-Sched Overview The ORT8850 includes three byte-wide, full-duplex DDR RapidIO interfaces running at up to 311 MHz (622 Mbits/s) per line for a total of 5.0 Gbits/s for each interface. Each input and output interface includes byte-wide data, one control signal (such as start-ofcell), and one clock signal. One of the three RapidIO interfaces is always available. The other two RapidIO interface are available only if the eight CDR channels are not being used. One function of the ORT8850 is to interface with the protocol independent scheduler (Pi-Sched) device on a port card. The Pi-Sched IC is part of the high-speed switching (HSSW) family of devices. It offers a highly integrated, innovative, and complete VLSI solution for implementing the scheduling and buffer management functionality of a cell (e.g., ATM) or packet (e.g., IP) switching system port at OC-48c. The RapidIO in the ORT8850 will support the dedicated receive and transmit interfaces for off-chip communication. Both interfaces drive or receive off-chip through LVDS I/O pads. The LVDS I/Os are fully terminated on-chip to allow for driving high-speed parallel backplanes at speeds up to 311 MHz. Internally, each 8-bit RapidIO interface is connected to a 32-bit interface which is single-edge clocked and connected to the 34 One LVDS clock pair running at 120 MHz--311 MHz. Its relationship is intended to be in the eye of the receive cell data. One LVDS start-of-cell pair, which indicates that word 0 of a data cell is on the receive data port. Eight LVDS data pairs, double-edge clocked by the LVDS clock. s s The eight LVDS data pairs are double-edge clocked by the LVDS receive clock (RXCLK). The RXCLK is aligned to the center of the eye of the received data and start-of-cell (RXD and RXSOC). To achieve optimal timing margin, the receiver is required to maintain this alignment. The RapidIO interface requires that the SOC spacing is an integer multiple of two clock cycles for proper operation and that SOCs occur only on the rising edge of the receive clock (RXCLK). Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver RapidIO Interface to Pi-Sched (continued) REPEATED 7 TIMES (ONE FOR EACH OF RXD[1:7]) 133 MHz CLOCK DOMAIN 266 MHz CLOCK DOMAIN D INPUT DATA CAPTURE D Q D CK CK SHIFT REGISTERS Q D CK Q D CK Q ZRXD_23 TO FPGA Q CK ZRXD_15 ZRXD_31 Q ZRXD_7 CLK RXD[0] D D Q Q CK D CK Q D CLK RXD[7] D CK Q RXSOC D CK Q WRXCLK (133 MHz) D RXCLK Q D Q D Q D Q ZRXSOC 0676 Figure 14. RapidIO Receive Cell Interface Octets and Start of Cell Cells will be transmitted on the high-speed LVDS inputs as octets. The first octet o0 (consisting of d0_0, d1_0 . . . d7_0) will be present on bits 31:24 on the low-speed 32-bit FPGA bus. Similarly, octet o1 (consisting of d0_1, 1_1 . . . d7_1) will be present on bits 23:16 on the 32-bit bus. Thus, octets will always be transmitted from first octet to last. The minimum number of octets present on the high-speed ports should always be divisible by 4, evenly representing the relationship with the 32-bit core of the ASIC interface. The start-of-cell signal is always aligned with the first octet of each cell. Once the first octet of a cell is received, subsequent octets are part of an uninterrupted data stream until the entire cell has been received. The number of octets in a cell is determined by the register bits OCELLSIZE. The RapidIO can support varying minimum cell sizes from four octets up to 124 in increments of 4. The RapidIO is programmed with the cell size by writing to the OCELLSIZE register via the microprocessor interface. If the transmitted cell size is less than the programmed cell size, a violation occurs and the IRXSOCVIOL flag is active. This flag can be ignored if a given minimum cell size is not needed. Agere Systems Inc. 35 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 RapidIO Interface to Pi-Sched (continued) EVEN BYTE POSITIVEEDGE FLOPS UTXD [31:0] UTXSOC WUTXCLK (60 MHz--146 MHz) COMMON TRANSMIT FIFO ODD BYTE NEGATIVEEDGE FLOPS EVEN BYTE OUTPUT PORT DATA ALIGNMENT MUXes TXD[7:0] ODD BYTE OUTPUT PORT DATA ALIGNMENT MUXes INTERFACE 0677 32 TO 8 MUX CONTROLLER OUTPUT PORT CLOCK ALIGNMENT MUX TXCLK SOC INPUT SOC REGISTER OUTPUT PORT SOC ALIGNMENT MUX TXSOC PFCLK (4x OUTPUT CLOCK FROM PLL) (240 MHz--584 MHz) PLL Figure 15. RapidIO Transmit Cell Interface Transmit Cell Interface The transmit interface performs multiplexing of 32 bits of low-speed data onto four sequential octets of eight pairs of LVDS signal pins using both edges of a high-speed clock. The transmitter module consists of the following ten LVDS signal pairs (see Figure 15): s Eight LVDS data pairs (TXD), double-edge clocked by the LVDS clock TXCLK. The data pairs carry biphase data at 120 MHz--311 MHz. One start-of-cell LVDS pair that indicates that octet 0 of a data cell is on TXD. The transitions of this signal are at 90 degrees also with the crossing points of the LVDS clock (TXCLK). One LVDS clock pair output TXCLK operating at 120 MHz--311 MHz. Its relationship is intended to be exactly in 90 degree phase with the transitions of TXD data and TXSOC. s s The high-speed data outputs (TXD[0:7]) as well as the start-of-cell signal TXSOC are generated as a result of the positive edge of PFCLK. This is accomplished by multiplexing between the even and odd bytes of the data at a 1/2 PFCLK rate. PFCLK is derived from the internal PLL and operates at 4x the base frequency or between 240 MHz and 284 MHz. The PFCLK is expected to have a duty cycle of 47% to 53% with no more than 150 ps of jitter. The duty cycle of PFCLK will directly affect the accuracy of the high-speed clock and its ability to maintain the eye of the data. The 90 degree phase shift of the output clock puts TXCLK in the eye of the data. 36 Agere Systems Inc. OFF-CHIP FPGA I/F Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver RapidIO Interface to Pi-Sched (continued) Table 8. RapidIO Signals to/from FPGA Interface Name (All End with _A, _B, or _C Depending on Channel) Receive Cell Interface ZRXD<31:0> From FPGA To FPGA Description -- 32 ZRXSOC ZRXSOCVIOL -- -- 1 1 ZRXALNVIOL -- 1 ZCLKSTAT -- -- CSYSENB 1 -- RSTN_RX WRXCLK_[chan]_FPGA Transmit Cell Interface UTXD[31:0] 1 -- 32 -- 1 -- 32-bit data from the receive module. The bus contains four octets and reflects data received via the high-speed RXD data bus. Indicates the presence of the first octet of a new cell within the first 32-bit data word on the bus RXD in bit positions [31:24]. Indicates a minimum cell violation within the receive module. This signal will transition active-high coincident with RXSOC. An active state signals the new cell overran the previous cell, and the previous cell is in violation of the minimum cell size. Signals an alignment error. An active state signals RXSOC was captured on a negative RXCLK edge. The violation condition on this signal will stay high for a single WRXCLK_[chan]_FPGA cycle coincident with RXSOC. Indicates the loss or absence of a clock on the LVDS clock (RXCLK). This signal will be present for the duration of the absence of the clock, following a period to validate its absence. System cell processing enable. After reset is released, drive this signal high when the RapidIO is ready to transmit cells. This signal should be active after all control signals into the RapidIO are stable. Synchronous reset for all memory elements clocked by WRXCLK_[chan]_FPGA (derived from PLL). Derived from high-speed LVDS clock RXCLK (RXCLK/2). Transmit data bs containing four octets synchronized with the rising edge of the 60 MHz--146 MHz WUTXCLK_FPGA (derived from PLL) is clocked into the transmit FIFO within the RapidIO. UTXSOC 1 -- Start of cell, originating within core, synchronized with the rising edge of WUTXCLK_FPGA into the transmit FIFO. Indicates the first data word on TXD bus includes the first octet of a new cell in bit positions [31:24]. RSTN_UTX 1 -- Synchronous reset for all memory elements in the WUTXCLK domain. UTXTRISTN 1 -- Output 3-state enable (active-low). When active, the TXD, TXSOC, and TXCLK LVDS drivers are 3-stated. 0: 3-state TXD, TXSOC and TXCLK drivers. 1: Normal operation. FPGA Interface Clocks (Common to All Channels) WUTXCLK_FPGA -- 1 One X core clock generated from an internal PLL circuit. Synchronous to UTXD and UTXSOC data inputs. HALFCLK_FPGA -- 1 1/2 X main PLL output clock. Phase-aligned with PFCLK. Nominal frequency = 30 MHz to 73 MHz. Duty cycle spec = 47%/ 53%. 37 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 RapidIO Interface to Pi-Sched (continued) Table 9. Signals Used as Register Bits Register Bit(s) OSHLBENB Description Used during the internal built-in self-test mode. Indicates that the single-ended versions of the transmit module outputs should be looped back into the single-ended inputs of the receive module. OSHLENB = 0: No loopback. OSHLENB = 1: Loopback. OCELLSIZE[4:0] This value indicates the minimum cell size and will be used to detect cell underrun errors. This value should be set and stable prior to initialization of operation and stable thereafter. OTESTENB Enables the internal self-test of the RapidIO block. Two loopback paths exist during test, internal and external. During both tests, data is passed through all modules and verified. ITESTDONE Indicates the completion of the internal test. Only valid during a test when OTESTENB is high. ITESTDONE = 0: Test running. ITESTDONE = 1: Test complete. ITESTPASS Indicates the success of the internal test. This signal is valid only when ITESTDONE is high. ITESTPASS = 0: Test failed. ITESTPASS = 1: Test passed. TRISTN Active-low. 3-state override for transmit outputs. This signal is ignored during reset, but takes priority over all 3-state control signals when active. Memory Map Definition of Register Types There are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. There are no mixed registers in the chip. This means that all bits of a particular register (particular address) are structurally the same. All of these registers are accessed via the FPGA system bus which, in turn, can be accessed by the MPI block or through FPGA logic. 38 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 10. Structural Register Elements Element sreg Register Status Register Description creg preg iareg isreg ereg A status register is read only, and, as the name implies, is used to convey the status information of a particular element or function of the ORT8850 core. The reset value of an sreg is really the reset value of the particular element or function that is being read. In some cases, an sreg is really a fixed value; an example of which is the fixed ID and revision registers. Control A control register is read and writable memory element inside core control. The value of Register a creg will always be the value written to it. Events inside the ORT8850 core cannot affect creg value. The only exception is a soft reset, in which case the creg will return to its default value. Pulse Each element, or bit, of a pulse register is a control or event signal that is asserted and Register then deasserted when a value of one is written to it. This means that each bit is always of value 0 until it is written to, upon which it is pulsed to the value of one and then returned to a value of 0. A pulse register will always have a read value of 0. Interrupt Alarm Each bit of an interrupt alarm register is an event latch. When a particular event is proRegister duced in the ORT8850 core, its occurrence is latched by its associated iareg bit. To clear a particular iareg bit, a value of one must be written to it. In the ORT8850 core, all isreg reset values are 0. Interrupt Status Each bit of an interrupt status register is physically the logical-OR function. It is a conRegister solidation of lower-level interrupt alarms and/or isreg bits from other registers. A direct result of the fact that each bit of the isreg is a logical-OR function means that it will have a read value of one if any of the consolidation signals are of value one, and will be of value 0 if and only if all consolidation signals are of value 0. In the ORT8850 core, all isreg default values are 0. Interrupt Enable Each bit of a status register or alarm register has an associated enable bit. If this bit is Register set to value one, then the event is allowed to propagate to the next higher level of consolidation. If this bit is set to zero, then the associated iareg or isreg bit can still be asserted but an alarm will not propagate to the next higher level. An interrupt enable bit is an interrupt mask bit when it is set to value 0. Registers Access and General Description The memory map comprises three address blocks: s s s Generic register block: ID, revision, scratch pad, lock, FIFO alignment, and reset registers. Device register block: control and status bits, common to the four channels in each of the two quad interfaces. Channel register blocks: each of the four channels in both quads have an address block. The four address blocks in both quads have the same structure, with a constant address offset between channel register blocks. All registers are write-protected by the lock register, except for the scratch pad register. The lock register is a 16-bit read/write register. Write access is given to registers only when the key value 0x0580 is present in the lock register. An error flag will be set upon detecting a write access when write permission is denied. The default value is 0x0000. After powerup reset or soft reset, unused register bits will be read as zeros. Unused address locations are also read as zeros. Write-only register bits will be read as zeros. The detailed information on register access and function are described on the tables, memory map, and memory map bit description. A memory map is included in Table 11, followed by detailed descriptions in Table 11. These tables list only the memory map for the core registers of the ORT8850 device. The remaining FPGA registers can be found in the Series 4 data sheet. Agere Systems Inc. 39 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) This table is constructed to show the correct values when read and written via the system bus MPI interface. When using this table while interfacing with the system bus user logic master interface, the data values will need to be byte flipped. This is due to the opposite orientation of the MPI and master interface bus ordering. More information on this can be found in the MPI/System Bus Application Note (AP01-032NCIP). Table 11. Memory Map (This table resides at memory offset 0X30000 in the ORT8850.) ADDR [7:0] 00 01 02 03 04 05 06 Register Type sreg sreg sreg creg creg creg preg -- -- -- DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB Reset Value [7:0] 05 80 80 00 00 00 -- -- global reset comman d lvds lpbk control (CDR only) device reg. blk - rx NA generic register block Comment fixed rev [0:7] fixed id lsb [0:7] fixed id msb [0:7] scratch pad [0:7] lockreg msb [0:7] lockreg lsb [0:7] -- -- Device Register Block 08 creg -- -- -- "rx toh frame" and "rx toh clk enable" hiz control ext prot sw en -- -- 00 09 creg 0a 0b 0c creg creg creg serial serial parallel serial port parallel serial parallel parallel FF (4 ch was 0F) port port port port output port port port output output output output MUX output output output MUX MUX MUX MUX select for MUX MUX MUX select for select for select for select for ch#5 select for select for select for ch#1 ch#3 ch#1 ch#3 ch#7 ch#5 ch#7 -- -- -- FIFO aligner threshold value (min) [0:4] 40 -- -- -- FIFO aligner threshold value (max) [0:4] A8 -- line lpbk number of consecutive A1 A2 errors to 06 input/ scrambler/ descrambler control output parallel bus parity control control generate [0:3] device reg blk - tx 0d 0e 0f creg creg creg a1 error insert value [0:7] a2 error insert value [0:7] transmitter B1 error insert mask [0:7] 00 00 00 40 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 11. Memory Map (continued) ADDR [7:0] 10 Register Type isreg DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB ch 1 int Reset Value [7:0] 00 Comment -- -- -- per device int -- ch 4 int ch 3 int ch 2 int 11 12 iereg iareg -- -- -- -- -- -- top-level interrupts enable/mask register [0:4] -- -- write to locked register error flag 00 frame offset error flag 00 13 14 15 16 iereg isreg iereg creg -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ch 8 int STM-A mode control -- ch 7 int STM-A mode control enable/mask register [6:7] ch 6 int STM-B mode control ch 5 int STM-B mode control 00 00 00 0x00 -- enable/mask register [0:3] 17 creg 18 creg STM A Stream A resync. -- STM B STM B STM B STM B STM A STM A STM A Stream Stream C Stream Stream Stream Stream B Stream C resync D resync A resync B resync resync D resync resync STM A STM A Resync and B (all 4 resync streams (all 8 streams AA, AB, AA to BD) AC and AD) hi-z control of parallel output bus channel enable/ disable control STM B Resync (all 4 streams BA, BB, BC and BD) parallel output bus parity err ins cmd tx k1 k2 source select tx d5 source select -- Twins Twins Twins CC Twins DD resync BB AA (streams resync resync Resync (streams (streams AC and (streams AD and BC) AA and AB and BD) BB) BA) 00 -- 00 -- Channel Register Block 20, 38, 50, 68, 80, 98, b0, c8 creg hi-z control of TOH data output rx k1/k2 source select TOH serial output port par err ins cmd tx d11 source select tx d3 source select disable B1 insert force ais-l rx control behavior in lof 80 rx control signals 21, 39, 51, 69, 81, 99, b1, c9 22, 3a, 52, 6a, 82, 9a, b2, ca 23, 3b, 53, 6b, 83, 9b, b3, cb creg tx e1 f1 tx mode e2 source of select operatio n tx d8 source select -- tx d7 source select -- tx s1 m0 source select tx d6 source select -- tx d12 source select tx d4 source select disable A1/A2 insert tx d10 source select tx d2 source select b1 error insert comman d tx d9 source select tx d1 source select a1 a2 error ins comman d 00 tx control signals creg 00 creg 00 Agere Systems Inc. 41 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) Table 11. Memory Map (continued) ADDR [7:0] 24, 3c, 54, 6c, 84, 9c, b4, cc 25, 3d, 55, 6d, 85, 9d, b5, cd 26, 3e, 56, 6e, 86, 9e, b6, ce 27, 3f, 57, 6f, 87, 9f, b7, cf 28, 40, 58, 70, 88, a0, b8, d0 29, 41, 59, 71, 89, a1 b9, d1 Register Type sreg DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB Concat indication 3 Concat indication 1 per sts-12 alarm flag Reset Value [7:0] NA per sts#1 cos flag Comment -- -- -- -- Concat indication 12 Concat indication 10 -- Concat indication 9 Concat indication 7 elastic store overflow flag Concat indication 6 Concat indication 4 ais-p flag sreg Concat indication 11 -- Concat indication 8 -- Concat indication 5 -- Concat indication 2 -- NA isreg 00 per channel interrupt consolidation iereg -- -- -- -- -- enable/mask register [0:3] 00 iareg -- FIFO (Out of Sync) error flag -- TOH serial input port parity error flag input parallel bus parity error flag LVDS link B1 parity error flag LOF flag Receiver internal path parity error flag FIFO* aligner threshold error flag 00 per sts-12 interrupt flags iereg -- enable/mask register [0:5] 00 * The FIFO aligner threshold error flag is only valid if a FIFO out of sync error flag is also present. 42 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 11. Memory Map (continued) ADDR [7:0] 2a, 42, 5a, 72, 8a, a2, ba, d2 2b, 43, 5b, 73, 8b, a3, bb, d3 2c, 44, 5c, 74, 8c, a4, bc, d4 iereg iareg AIS interrupt flag 11 -- AIS interrupt flag 8 -- AIS interrupt flag 5 -- AIS interrupt flag 2 -- Register Type iareg DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB AIS interrupt flags 3 AIS interrupt flag 1 enable/ mask AIS interrupt flags 3 enable/ mask AIS interrupt flag 1 ES overflow flags 3 ES overflow flag 1 00 -- 00 00 00 00 per sts-1 interrupt flags 00 Reset Value [7:0] 00 Comments -- -- -- -- AIS interrupt flags 12 AIS interrupt flag 10 enable/ mask AIS interrupt flags 12 enable/ mask AIS interrupt flag 10 ES overflow flags 12 AIS interrupt flag 9 AIS interrupt flag 7 enable/ mask AIS interrupt flag 9 enable/ mask AIS interrupt flag 7 ES overflow flag 9 ES overflow flag 7 AIS interrupt flags 6 AIS interrupt flag 4 enable/ mask AIS interrupt flags 6 enable/ mask AIS interrupt flag 4 ES overflow flags 6 ES overflow flag 4 2d, 45, 5d, 75, 8d, a5, bd, d5 iereg enable/ mask AIS interrupt flag 11 -- enable/ mask AIS interrupt flag 8 -- enable/ mask AIS interrupt flag 5 -- enable/ mask AIS interrupt flag 2 -- 2e, 46, 5e, 76, 8e, a6, be, d6 2f, 47, 5f, 77, 8f, a7, bf, d7 30, 48, 60, 78, 90, a8, c0, d8 31, 49, 61, 79, 91, a9, c1, d9 iareg iareg ES overflow flag 11 ES overflow flag 8 -- ES overflow flag 5 -- ES overflow flag 2 -- ES overflow flag 10 iereg -- enable/ enable/ enable/ enable/ mask ES mask ES mask ES mask ES overflow overflow overflow overflow flags flags flag flags 12 9 6 3 iereg enable/ enable/ enable/ enable/ enable/ enable/ enable/ enable/ mask ES mask ES mask ES mask ES mask ES mask ES mask ES mask ES overflow overflow overflow overflow overflow overflow overflow overflow flag flag flag flag flag flag flag flag 11 8 5 2 10 7 4 1 00 -- Agere Systems Inc. 43 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) Table 11. Memory Map (continued) ADDR [7:0] 32, 4a, 62, 7a, 92, aa, c2, da 33, 4b, 63, 7b, 93, ab, c3, db 34, 4c, 64, 7c, 94, ac, c4, dc 35, 4d, 65, 7d, 95, ad, c5, dd 36, 4e, 66, 7e, 96, ae, c6, de 37, 4f, 67, 7f, 97, af, c7, df CDR Specific Registers e0 e3 f0 creg creg creg -- RapidIO OPIMODE (shim) (Reserved) Loopback enable -- -- -- -- TST MODE BYPASS LOOP BKEN TST PHASE -- EN10BIT Shim Mode -- -- -- -- -- -- creg -- -- Framer Disable Sync control LVDS redundant select Bypass Alignment FIFO + Pointer Mover Bypass Pointer Mover 00 -- counter Sampler phase error count 00 -- Register Type counter DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB Reset Value [7:0] 00 Comments overflow LVDS link b1 BIP-8 parity error counter counter overflow LOF counter 00 binning counter overflow A1 A2 frame error counter 00 creg Reserved -- -- FIFO depth register 0x0c -- ENCOMMA[0:7] OCELLSIZE[3:7] Pi-Sched Registers f1 f2 sreg creg -- -- -- -- -- -- -- -- ITESTDO NE IBYPASS ITEST PASS OTEST ENB 0 -- -- -- 44 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions Bit/Register Name(S) fixed rev [0:7] fixed id lsb [0:7] fixed id msb [7:0] scratch pad [0:7] lockreg msb [0:7] lockreg lsb [0:7] Bit/ Reset Register Register Value Location Type (Hex) (Hex) 00 [0:7] 01 [0:7] 02 [0:7] 03 [0:7] 04 [0:7] 05 [0:7] sreg 05 80 80 00 00 00 NA Description creg creg global reset command 06 [0] preg NA The scratch pad has no function and is not used anywhere in the core. However, this register can be written to and read from. In order to write to registers in memory locations 06~7F, lockreg msb and lockreg lsb must be respectively set to the values of 05 and 80. If the msb and lsb lockreg values are not set to {05, 80}, then any values written to the registers in memory locations 06~7F will be ignored. After reset (both hard and soft), the core is in a write locked mode. The core needs to be unlocked before it can be written to. Also note that the scratch pad register (03) can always be written to as it is unaffected by write lock mode. The global reset command is accessed via the pulse register in memory address 06. The global reset command is a soft (software initiated) reset. Nevertheless, the global reset command will have the exact reset effect as a hard (RST_N pin) reset. Device Register Blocks lvds lpbk control 08 [0] creg 0 CDR 0 1 No loopback. LVDS loopback, transmit to receive on. Serieal data is looped back to the rx serial input. ext prot sw en 08 [3] creg 0 ext port sw en 0 LVDS Protection Switching - MUX is controlled by software (1 control bit per MUX) reg 09. - Output buffers' enables are controlled by software (1 control bit per channel) reg 20, 38, 50, 68, 80, 98, b0, c8. MUX is controlled by hardware pins. lvds_Prot_Switch_[aa,ab,ac,ad,ba,bb,bc,bd] 1 "rx toh frame" and "rx toh clk enable" hiz control 08 [4] creg 0 0 1 TOH_CK_FP_EN = 0, can be used to 3-state RX_TOH_CK_EN and RX_TOH_FP signals. Function mode. Agere Systems Inc. 45 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Name(S) Bit/ Register Register Reset Location Type Value (Hex) (Hex) creg 1 09 [0] 1 1 09 [1] 1 09 [2] 09 [3] 09 [4] 09 [5] 09 [6] 09 [7] 0A [0:4] 0B [0:4] creg 40 A8 These are the minimum and maximum thresholds values for the per channel receive direction alignment FIFOs. If and when the minimum or maximum threshold value is violated by a particular channel, then the interrupt event "FIFO aligner threshold error" will be generated for that channel and latched as a "FIFO aligner threshold error flag" in the respective per STS-12 interrupt alarm register. The allowable range for minimum threshold values is 1 to 23. The allowable range for maximum threshold values is 0 to 22. Note that the minimum and maximum FIFO aligner threshold values apply to all four channels. These three per device control signals are used in conjunction with the per channel "a1 a2 error insert command" control bits to force A1 A2 errors in the transmit direction. If a particular channel's "a1 a2 error insert command" control bit is set to the value 1 then the "A1 and A2 error insert values" will be inserted into that channels respective A1 and A2 bytes. The number of consecutive frames to be corrupted is determined by the "number of consecutive A1 A2 errors to generate[0:3]" control bits. The error insertion is based on a rising edge detector. As such the control must be set to value 0 before trying to initiate a second a1 a2 corruption. 0 1 No loopback. rx to tx loopback on backplane side. Serial input is run through SERDES and looped back in parallel to SERDES and out serial. Description serial port output MUX select for ch#1 serial port output MUX select for ch#3 parallel port output MUX select for ch#1 parallel port output MUX select for ch#3 serial port output MUX select for ch#5 parallel port output MUX select for ch#7 serial port output MUX select for ch#5 parallel port output MUX select for ch#7 FIFO aligner threshold value (min) Default = 2 FIFO aligner threshold value (max) Default = 15 serial port output MUX 0 1 parallel port output 0 1 Parallel output data bus is multiplexed to next channel. Parallel output data bus is multiplexed to same channel TOH output is multiplexed to next channel. TOH output is multiplexed to same channel. number of consecutive A1 A2 errors to generate [0:3] A1 error insert value [0:7] A2 error insert value [0:7] 0C [0:3] 0D [0:7] 0E [0:7] creg 00 00 00 backplane side loopback control 0C [4] creg 0 46 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Reset Register Register Value Location Type (Hex) (Hex) 0C [5] creg 1 0 1 Even parity. Odd parity. Bit/Register Name(S) Description input/output parallel bus parity control scrambler/descrambler control 0C [6] creg 1 0 1 no rx direction, descramble / tx direction scramble. In rx direction, descramble channel after SONET frame recovery. In tx direction, scramble data just before parallel-to-serial conversion. transmit B1 error insert mask [0:7] ch 1 int ch 2 int ch 3 int ch 4 int per device int enable/mask register for ch 1-4 + device[4:0] ch 5 int ch 6 int ch 7 int ch 8 int enable/mask register for ch 5-8 [0:3] frame offset error flag write to locked register error flag enable/mask register [0:1] 0F [0:7] creg 00 0 1 No error insertion. Invert corresponding bit in B1 byte. 10 [0] 10 [1] 10 [2] 10 [3] 10 [4] 11 [0:4] 14 [0] 14 [1] 14 [2] 14 [3] 15 [0:3] 12 [0] 12 [1] 13 [0:1] isreg isreg isreg isreg isreg iereg isreg isreg isreg isreg iereg 0 0 0 0 0 0 0 0 0 0 0 Consolidation interrupts. 1 = interrupt, 0 = no interrupt. iareg iareg iereg 0 0 0 If in the receive direction the phase offset between any two channels exceeds 17 bytes, then a frame offset error event will be issued. This condition is continuously monitored. If the core memory map has not been unlocked (by writing to the lock registers), and any address other than the lockreg registers or scratch pad register is written to, then a "write to locked register" event will be generated. 00 - Quad STS-12 or STS-48. 01 - Quad STS-3. 10 - Quad STS-1. 00 - Quad STS-12 or STS-48. 01 - Quad STS-3. 10 - Quad STS-1. Write 1 to resync stream. Write 1 to resync selected grouping. STM A mode control 16 [2:3] creg 0 STM B mode control 16 [0:1] creg 0 individual alignment resync register group alignment resync register 17 [0:7] 18 [0:7] creg creg 0 0 Agere Systems Inc. 47 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Location (Hex) 20, 38, 50, 68, 80, 98, b0, c8 [0] 20, 38, 50, 68, 80, 98, b0, c8 [1] 20, 38, 50, 68, 80, 98, b0, c8 [2] 20, 38, 50, 68, 80, 98, b0, c8 [3] 20, 38, 50, 68, 80, 98, b0, c8 [4] Register Type Reset Value (Hex) Bit/Register Name(S) Channel Register Blocks rx behavior in lof Description -- 1 rx behavior in log 0 When Rx direction OOF occurs, do not insert AIS-L. When Rx direction OOF occurs, insert AIS-L. 0 1 force ais-l control force ais-l control 0 1 Do not force AIS-L. Force AIS-L. TOH serial output port par err ins cmd -- 0 0 1 Do not insert a parity error. Insert parity error in parity bit of receive TOH serial output for as long as this bit is set. rx k1/k2 source select -- 0 0 1 Set receive direction K2 K2 bytes to 0. Pass receive direction K1 K2 though pointer mover. parallel output bus parity err ins cmd -- 0 0 1 Do not insert parity error. Insert parity error in the parity bit of receive direction parallel output bus for as long as this bit is set. channel enable/disable control 20, 38, 50, 68, 80, 98, b0, c8 [5] hi-z control of parallel output bus 20, 38, 50, 68, 80, 98, b0, c8 [6] creg 0 channel enable / disable control creg 0 0 Power down CDR channels (PWR_DN_A/B/C/ D_N=0). TOH_EN_A(or B, C, D)=0, and DOUTA(or B, C, D)=0, can be used to 3-state output buses. Functional mode. creg 0 1 hi-z control of parallel output bus 0 1 hi-z control of TOH data output 0 hi-z control of TOH data output 20, 38, 50, 68, 80, 98, b0, c8 [7] DOUTA(or B, C, D) _EN=0, can be used to 3-state output bus. Functional mode. TOH_EN_A(or B, C, D)=0, can be used to 3-state TOH output lines. 48 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Name(S) tx mode of operation Bit/Register Location (Hex) 21, 39, 51, 69, 81, 99, b1, c9 [7] 21, 39, 51, 69, 81, 99, b1, c9 [6] 21, 39, 51, 69, 81, 99, b1, c9 [5] 21, 39, 51, 69, 81, 99, b1,c9 [4:0] Register Type creg Reset Value (Hex) 0 Tx mode of operation: 0 1 Insert TOH from serial ports on FPGA interface. Pass through all TOH of parallel stream. Description tx e1 f2 e2 source select creg 0 Other registers: 0 1 Insert TOH from serial ports on FPGA interface. Pass through that particular TOH byte. tx s1 m0 source select creg 0 tx k1 k2 source select creg 0 tx d12~d9 source select tx d8~d1 source select a1 a2 error insert command 22, 3a, 52, 6a, 82, 9a, b2, ca [7:0] 23, 3b, 53, 6b, 83, 9b, b3, cb [0] 23, 3b, 53, 6b, 83, 9b, b3, cb [1] 23, 3b, 53, 6b, 83, 9b, b3, cb [2] 23, 3b, 53, 6b, 83, 9b, b3, cb [3] 24, 3c, 54, 6c, 84, 9c, b4, cc [0:3] 25, 3d, 55, 6d, 85, 9d, b5, cd [0:7] creg 00 creg 0 0 1 Do not insert error. Insert error for number of frames in register hex 0C. b1 error insert command creg 0 The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second a1 a2 corruption. 0 1 Do not insert error. Insert error for 1 frame in B1 bits defined by register hex 0F. disable b1 insert The error insertion is based on a rising edge detector. As such, the conrtol mustbe set to value 0 before trying to initiate a second disable a1 insert concat indication 12, 9, 6, 3 sreg 0 The value 1 in any bit location indicates that STS# is in CONCAT mode. A 0 indicates that the STS in not in CONCAT mode, or is the head of a concat group. concat indication 11, 8, 5, 2, 10, 7, 4, 1 sreg 0 Agere Systems Inc. 49 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Location (Hex) 26, 3e, 56, 6e, 86, 9e, b6, ce [0] 26, 3e, 56, 6e, 86, 9e, b6, ce [1] 26, 3e, 56, 6e, 86, 9e, b6,ce [2] 27, 3f, 57, 6f, 87, 9f, b7, cf [5:7] Register Type isreg Reset Value (Hex) 0 Bit/Register Name(S) per sts-12 alarm flag Description These flag register bits per STS-12 alarm flag, ais-p flag, and elastic store overflow flag are the per-channel interrupt status (consolidation) register. ais-p flag isreg 0 elastic store overflow flag isreg 0 enable/mask register [0:5] iereg 0 50 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Name(S) FIFO aligner threshold error flag Bit/Register Location (Hex) 28, 40, 58, 70, 88, a0, b8, d0 [0] Register Type iareg Reset Value (Hex) 0 Description These are the per STS-12 alarm flags. receiver internal path par- 28, 40, 58, 70, 88, a0, b8, d0 [1] ity error flag LOF flag 28, 40, 58, 70, 88, a0, b8, d0 [2] 28, 40, 58, 70, 88, a0, b8, d0 [3] 28, 40, 58, 70, 88, a0, b8, d0 [4] iareg 0 iareg 0 Loss of frame. LVDS link B1 parity error flag input parallel bus parity error flag iareg 0 iareg 0 28, 40, 58, 70, TOH serial input port par88, a0, b8, d0 [5] ity error flag FIFO OOS error flag 28, 40, 58, 70, 88, a0, b8, d0 [6] 29, 41, 59, 71, 89, a1, b9, d1 [0:5] iareg 0 FIFO out of Sysc error flag. enable/mask register [0:5] iereg 00 Agere Systems Inc. 51 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Name(S) Bit/Register Location (Hex) Register Type iareg Reset Value (Hex) 0 Description These are the AIS-P alarm flags. 1 if the serial input stream contains AIS. AIS interrupt flags 12, 9, 6, 3 2a, 42, 5a, 72, 8a, a2, ba, d2 [0:3] AIS interrupt flags 11, 8, 5, 2, 10, 7, 4, 1 2b, 43, 5b, 73, 8b, a3, bb, d3 [0:7] 2c, 44, 5c, 74, 8c, a4, bc, d4 [0:3] iareg 00 enable/mask register 12, 9, 6, 3 iereg 0 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2d, 45, 5d, 75, 8d, a5, bd, d5 [0:7] ES overflow flags 12, 9, 6, 3 2e, 46, 5e, 76, 8e, a6, be, d6 [0:3] ES overflow flags 11, 8, 5, 2, 10, 7, 4, 1 2f, 47, 5f, 77, 8f, a7, bf, d7 [0:7] 30, 48, 60, 78, 90, a8, b0, d8 [0:3] 31, 49, 61, 79, 91, a9, b1, d9 [0:7] iereg 00 iareg 0 These are the elastic store overflow alarm flags. iareg 00 enable/mask register 12, 9, 6, 3 iereg 0 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 iereg 00 52 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Location (Hex) Register Type counter Reset Value (Hex) 00 Bit/Register Name(S) LVDS link b1 parity error counter Description 7 bit count + overflow - reset on read. 32, 4a, 62, 7a, 92, aa, b2, da [0:7] LOF counter 33, 4b, 63, 7b, 93, ab, b3, db [0:7] A1 A2 frame error counter 34, 4c, 64, 7c, 94, ac, b4, dc [0:7] FIFO depth register 35, 4d, 65, 7d, 95, ad, c5, dd [3:7] Sampler phase error 36, 4e, 66, counter 7e, 96, ae, c6, de [0:7] Bypass register 37, 4f, 67,7f, 97, af, c7, df[0] Bypass register 37, 4f, 67, 7f, 97, af, c7, df[1] Enable work/protect chan- 37, 4f, 67, nels 7f, 97, af, c7, df[2] counter 00 7 bit count + overflow - reset on read increments on a change from in-frame to out-of-frame state. counter 00 7 bit count + overflow - reset on read. sreg 30 30 indicates FIFO is half full. counter 00 Write 1 to clear. creg 0 1: Bypass pointer mover. creg 0 1: Bypass alignment FIFO + pointer mover. creg 0 Sync control register 37, 4f, 67, 7f, 97, af, c7, df[3:4] 37, 4f, 67, 7f, 97, af, c7, df[5] creg 00 Disable framer creg 0 Bit to control the LVDS drivers/receivers to/from CDR. 0: Use LVDS drivers and receivers to/from Pi-sched I/F block B (work channels). 1: Use LVDS drivers and receivers to/from Pi-sched I/F block C (protect channels). 00: No alignment. 01: Align with twin (i.e., STM B stream A). 10: Align with all 4 (i.e., STM A all streams). 11: Align with all 8 (i.e., STM A and B all streams). 0: Enable framer. 1: Disable STS-12 framing. Agere Systems Inc. 53 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Location (Hex) 0xe0[6] Register Type creg Reset Value (Hex) 0 Bit/Register Name(S) CDR control register 1 Description Enables CDR test mode. Initiates CDR's built-in selftest: 0: Regular mode. 1: Test mode. Enables bypassing of the 622 MHz clock synthesis with TSTCLK. 0: Use PLL. 1: Bypass PLL (uses TSTCLK as reference clock). Enables LVDS loopback. 0: No loopback. 1: Loopback. When set to 1, controls bypass of 16 PLL generated phases with 16 low-speed phases. EN10BIT. Sets 10 to 1 MUX/deMUX: 1 = 10:1 MUX/deMUX. 0 = 8:1 MUX/deMUX. 0 = Long-haul I/F mode (enables CDR + STM operation). 1 = Short-haul I/F mode (disables CDR, enables Pisched interfaces). Enables 10-bit Ethernet word alignment per channel. Used during internal built-in self-test mode: 0 = No loopback. 1 = Loopback. Reserved bit (read-only): 0 = Shuts down Bidi logic and ignores auxiliary bypass signals. Always set to 0. Indicates minimum cell size and will be used to detect cell underrun errors. Indicates completion of the internal test. Only valid when OTESTENB (0xf2[7] is high): 0 = Test running. 1 = Test complete. Indicates success of the internal test. Valid only when ITESTDONE is high: 0 = Test failed. 1 = Test passed. Enables bypass of the PLL circuit. TSTCLK is used in this mode. 1 = Enables internal self-test of the SHIM block. Both internal and external loopback paths exist during this test. 0xe0[5] creg 0 0xe0[4] creg 0 0xe0[3] CDR control register 1 0xe0[1] creg creg 0 0 0xe0[0] creg 0 CDR control register 4 Pi-Sched I/F Ctl register 0xe3[0:7] 0xf0[6] creg creg 0 0xf0[5] creg 0 0xf0[0:4] Pi-Sched I/F status register 0xf1[0] creg sreg 0xf1[1] sreg Pi-Sched I/F Ctl register 0xf2[0] 0xf2[1] creg creg 0 0 54 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series 3+ FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. Table 13. Absolute Maximum Ratings Parameter Storage Temperature Power Supply Voltage with Respect to Ground Symbol Tstg VDD33 VDDIO VDD15 VDDA_SHIM* VDDA_STM* Input Signal with Respect to Ground Signal Applied to High-impedance Output Maximum Package Body Temperature -- -- -- Min -65 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- Max 150 4.2 4.2 2.0 2.0 2.0 VDDIO + 0.3 VDDIO + 0.3 220 Unit C V V V V V V V C * VDDA_SHIM and VDDA_STM are analog power supply inputs which need to be isolated from other power supplies on the board. Recommended Operating Conditions Table 14. Recommended Operating Conditions Parameter Power Supply Voltage with Respect to Ground* Symbol VDD33 VDD15 VDDA_SHIM VDDA_STM Input Voltages Junction Temperature VIN TJ Min 2.7 1.4 1.4 1.4 -0.3 -40 Max 3.6 1.6 1.6 1.6 VDDIO + 0.3 125 Unit V V V V V C * For recommended operating conditions for VDDIO, see the Series 4 FPGA Data Sheet and the Series 4 I/O Buffer Application Note. VDDA_SHIM and VDDA_STM are analog power supply inputs which need to be isolated from other power supplies on the board. VDD33 is an analog power supply for the FPGA PLLs and needs to be isolated from other power supplies on the board. Agere Systems Inc. 55 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Power Supply Decoupling LC Circuit The 850 MHz HSI macro contains both analog and digital circuitry. The data recovery function, for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its 850 MHz reference frequency. The internal analog phase-locked loop contains a voltage-controlled oscillator. This circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic gates and parasitic inductive elements. Generated noise that contains frequency components beyond the bandwidth of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit elements. Additional power supply filtering in the form of a LC pi filter section will be used between the power supply source and these device pins as shown in Figure 16. The corner frequency of the LC filter is chosen based on the power supply switching frequency, which is between 100 kHz and 300 kHz in most applications. Capacitors C1 and C2 are large electrolytic capacitors to provide the basic cut-off frequency of the LC filter. For example, the cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capacitor C3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended filter for the HSI macro is shown below: L = 4.7 H, RL = 1 , C1 = 0.01 F, C2 = 0.01 F, C3 = 4.7 F. FROM POWER SUPPLY SOURCE L TO DEVICE VDDA_STM + C1 + C2 + C3 PLL_VSSA 5-9344(F) Figure 16. Sample Power Supply Filter Network for Analog HSI Power Supply Pins The Rapid IO interface to Pi-Sched also has internal PLLs that require an analog supply, VDDA_SHIM. The same power supply filter network shown above should be repeated and applied to the VDDA_SHIM inputs if this interface is used. If both the Rapid IO interface and the HSI interface are used, two seperate copies of this interface should be used. If the programmable PLLs on the FPGA potrion of the device are to be used, then the VDD33 supply must isolated in the same way. More information on this and other requirements for the FPGA PLLs can be found in the Series 4 PLL application note. 56 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver HSI Electrical and Timing Characteristics Table 15. Absolute Maximum Ratings Parameter Power Dissipation on VDDA_STM Conditions Eight channels Min -- Typ -- Max 385 Unit mW Table 16. Recommended Operating Conditions Parameter VDD15 Supply Voltage Junction Temperature Table 17. Receiver Specifications Parameter Input Data* Stream of Nontransitions Phase Change, Input Signal Eye Opening Jitter Tolerance Jitter Tolerance: 250 kHz 25 kHz 2 kHz Conditions -- Over a 200 ns time interval -- -- -- -- -- -- -- -- 0.6 6 60 UIp-p UIp-p UIp-p Min -- -- 0.4 Typ -- -- -- Max 60 100 -- Unit bits ps UIp-p Conditions -- TJ Min 1.4 -40 Typ -- -- Max 1.6 125 Unit V C * Scrambled data stream conforming to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence. --PN7 characteristic is 1 + X6 + X7. --PN9 characteristic is 1 + X4 + X9. Alternatively 8B/10B encoded data is also valid input data. This sequence should not occur more than once per minute. Translates to a frequency change of 500 ppm. A unit interval for 622.08 Mbits/s data is 1.6075 ns. Table 18. Transmitter Specifications Parameter Output Jitter, Generated Output Jitter, Generated (including I/O buffers) Table 19. Synthesizer Specifications Parameter PLL* Loop Bandwidth Jitter Peaking Powerup Reset Time Lock Aquisition Time Input Reference Clock Frequency Frequency Deviation Phase Change Conditions -- -- -- -- -- -- Over a 200 ns time interval Min -- -- 10 -- 62.5 -- -- Typ -- -- -- -- -- -- -- Max 6 2 -- 1 212.50 100 100 Unit MHz dB s ms MHz ppm ps Conditions 250 kHz to 5 MHz (measured with a spectrum analyzer) 250 kHz to 5 MHz Min -- -- Typ -- -- Max 0.15 0.25 Unit UIp-p UIp-p * External 10 k resistor to analog ground required. Translates to a frequency change of 500 ppm. Agere Systems Inc. 57 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Parallel RapidIO-like Interface Timing Characteristics Figure 17 illustrates the timing for the receive parallel interfaces A, B, and C (DDR). The recommended operating conditions for this interface are the same as for the HSI interface show in Table 16. Table 20 shows the worst case timing parameters for this interface made under these conditions. t1 P RXCLK N t2 N RXSOC RXD[7:0] P 5-9085.c(F) t3 Figure 17. Receive Parallel Data/Control Timing Table 20. Parallel Receive Data/Control Timing Symbol t1 -- -- t2 t3 Parameter Clock Frequency Clock Duty Cycle Clock Rise/Fall Time Data/Control Setup Time Required Data/Control Hold Time Required -1 Min -- 40 -- 290 290 Max 266 60 1.0 -- -- Min -- 40 -- 270 270 -2 Max 290 60 1.0 -- -- Min -- 40 -- 260 260 -3 Max 315 60 1.0 -- -- Unit MHz % V/ns ps ps Figure 18 illustrates the timing for the transmit parallel interfaces A, B, and C (DDR). The recommended operating conditions for this interface are the same as for the HSI interface shown in Table 16. Table 21 shows the worst case timing parameters for this interface under these conditions. t4 P TXCLK N t5 N TXSOC TXD[7:0] P 2289(F) t5 t5 t5 t5 t5 Figure 18. Transmit Parallel Data/Control Timing Table 21. Transmit Parallel Data/Control Timing Symbol t4 -- -- t5 58 Parameter Clock Frequency Clock Duty Cycle Clock rise/Fall Time Data Delay from Clock Edge -1 Min -- 45 -- 510 Max 266 55 1.0 -- Min -- 45 -- 510 -2 Max 290 55 1.0 -- Min -- 45 -- 510 -3 Max 315 55 1.0 -- Unit MHz % V/ns ps Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Embedded Core LVDS I/O Table 22. Driver dc Data* Parameter Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage Output Offset Voltage Output Impedance, Differential RO Mismatch Between A and B Change in Differential Voltage Between Complementary States Change in Output Offset Voltage Between Complementary States Output Current Output Current Power-off Output Leakage Symbol VOH VOL VOD VOS Ro RO VOD VOS ISA, ISB ISAB |Ixa|, |Ixb| Test Conditions RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% VCM = 1.0 V and 1.4 V VCM = 1.0 V and 1.4 V RLOAD = 100 1% RLOAD = 100 1% Driver shorted to GND Drivers shorted together VDD = 0 V VPAD, VPADN = 0 V--2.5 V Min -- 0.925 0.25 1.125* 80 -- -- -- -- -- -- Typ -- -- -- -- 100 -- -- -- -- -- -- Max 1.475 -- 0.45 1.275 120 10 25 25 24 12 10 Unit V V V V % mV mV mA mA mA * VDD33 = 3.1 V--3.5 V, VDD15 = 1.4 V--1.6 V, -40 C, and slow-fast process. External reference, REF10 = 1.0 V 3%, REF14 = 1.4 V 3%. Table 23. Driver ac Data* Parameter VOD Fall Time, 80% to 20% VOD Rise Time, 20% to 80% Differential Skew |tPHLA - tPLHB| or |tPHLB - tPLHA| Channel-to-channel Skew |tpDIFFm - tpDIFFn|, Propagation Delay Time Symbol tF tR tSKEW1 Test Conditions ZL = 100 1% CPAD = 3.0 pF, CPAD = 3.0 pF ZL = 100 1% CPAD = 3.0 pF, CPAD = 3.0 pF Any differential pair on package at 50% point of the transition Any two signals on package at 0 V differential ZL = 100 1% CPAD = 3.0 pF, CPADN = 3.0 pF Min 100 100 -- Typ -- -- -- Max 210 210 50 Unit ps ps ps tSKEW2 tPLH tPHL -- 0.54 0.55 -- 0.77 0.76 -- 1.10 1.09 ps ns ns * VDD33 = 3.1 V--3.5 V, VDD15 = 1.4 V--1.6 V, -40 C, and slow-fast process. Table 24. Driver Power Consumption* Parameter Driver dc Power Driver ac Power Symbol PDdc PDac Test Conditions ZL = 100 1% ZL = 100 1% CPAD = 3.0 pF, CPADN = 3.0 pF Min -- -- Max 26.0 64 Unit mW W/ MHz * VDD33 = 3.1 V--3.5 V, VDD15 = 1.4 V--1.6 V, -40 C, and slow-fast process. Agere Systems Inc. 59 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Embedded Core LVDS I/O (continued) LVDS Receiver Buffer Requirements Table 25. Receiver ac Data* Parameter Pulse-width Distortion Propagation Delay Time With Common-mode Variation (0 V to 2.4 V) Output Rise Time, 20% to 80% Output Fall Time, 80% to 20% * VDD = 3.1 V--3.5 V, 0 C --125 C, slow-fast process. Symbol tpwd tPLH tPHL tPD tR tF Test Conditions VIDTH = 100 mV, 450 MHz CL = 0.5 pF CL = 0.5 pF CL = 0.5 pF CL = 0.5 pF Min -- 0.60 0.60 -- 150 150 Max 160 1.41 1.47 50 350 350 Unit ps ns ns ps ps ps Table 26. Receiver Power Consumption* Parameter Receiver dc Power Receiver ac Power * VDD = 3.1 V--3.5 V, 0 C --125 C, slow-fast process. Symbol PRdc PRac Test Conditions dc ac CL = 0.5 pF Min -- -- Max 20.4 4.5 Unit mW W/ MHz Table 27. Receiver dc Data* Parameter Input Voltage Range, VIA or VIB Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance Symbol VI VIDTH VHYST RIN Test Conditions VGPD < 925 mV dc - 1 MHz VGPD < 925 mV 450 MHz (+VIDTHH) - (-VIDTHL) With build-in termination, center-tapped Min 0.0 -100 -- 80 Typ 1.2 -- -- 100 Max 2.4 100 -- 120 Unit V mV mV * VDD = 3.1 V--3.5 V, 0 C --125 C, slow-fast process. Table 28. LVDS Operating Parameters Parameter Transmit Termination Resistor Receiver Termination Resistor Temperature Range Power Supply VDD33 Power Supply VDD15 Power Supply VSS Test Conditions -- -- -- -- -- -- Min 80 80 -40 3.1 1.4 -- Normal 100 100 -- -- -- 0 Max 120 120 125 3.5 1.6 -- Unit C V V V Note:Under worst-case operating condition, the LVDS driver will withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. Similarly, when outputs are short-circuited to each other or to ground, the LVDS will not suffer permanent damage. The LVDS driver supports hot insertion. Under a well-controlled environment, the LVDS I/O can drive backplane as well as cable. 60 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Input/Output Buffer Measurement Conditions (on-LVDS Buffer) VCC GND TO THE OUTPUT UNDER TEST 50 pF TO THE OUTPUT UNDER TEST 1 k 50 pF A. Load Used to Measure Propagation Delay Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH. B. Load Used to Measure Rising/Falling Edges 5-3234(F) Figure 19. ac Test Loads ts[i] out[i] PAD ac TEST LOADS (SHOWN ABOVE) OUT VDD out[i] VDD/2 VSS PAD 1.5 V OUT 0.0 V TPLL TPHH 5-3233.a(F) Figure 20. Output Buffer Delays PAD IN in[i] 3.0 V PAD IN 1.5 V 0.0 V VDD in[i] VDD/2 VSS TPLL TPHH 5-3235(F) Figure 21. Input Buffer Delays Agere Systems Inc. 61 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 LVDS Buffer Characteristics Termination Resistor The LVDS drivers and receivers operate on a 100 differential impedance, as shown below. External resistors are not required. The differential driver and receiver buffers include termination resistors inside the device package, as shown in Figure 22 below. LVDS DRIVER LVDS RECEIVER 100 50 CENTER TAP 50 EXTERNAL DEVICE PINS 5-8703(F) Figure 22. LVDS Driver and Receiver and Associated Internal Components LVDS Driver Buffer Capabilities Under worst-case operating condition, the LVDS driver must withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. Similarly, when its outputs are short-circuited to each other or to ground, the LVDS driver will not suffer permanent damage. Figure 23 illustrates the terms associated with LVDS driver and receiver pairs. DRIVER INTERCONNECT RECEIVER VOA A AA VIA VOB B BB VIB VGPD 5-8704(F) Figure 23. LVDS Driver and Receiver CA VOA A RLOAD VOB B CB V VOD = (VOA - VOB) 5-8705(F) Figure 24. LVDS Driver 62 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information This section describes the pins and signals that perform FPGA-related functions. During configuration, the userprogrammable I/Os are 3-stated and pulled up with an internal resistor. If any FPGA function pin is not used (or not bonded to package pin), it is also 3-stated and pulled up after configuration. Table 29. FPGA Common-Function Pin Description Symbol Dedicated Pins VDD33 VDD15 VDDIO GND PTEMP RESET I/O -- 3 V positive power supply. Description -- 1.5 V positive power supply for internal logic. -- Positive power supply used by I/O banks. -- Ground supply. I I Temperature sensing diode pin. Dedicated input. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. As an input, a low level on DONE delays FPGA start up after configuration.* As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor. PRGM is an active-low input that forces the restart of configuration and resets the boundary scan circuitry. This pin always has an active pull-up. CCLK I O DONE I O PRGM RD_CFG I I This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0. RD_DATA/TDO CFG_IRQ/MPI_IRQ O O RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary scan, TDO is test data out. During JTAG, slave, master, and asynchronous peripheral configuration assertion on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output. * The FPGA States of Operation section contains more information on how to control these signals during start up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. Agere Systems Inc. 63 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 29. FPGA Common-Function Pin Description (continued) Symbol M[3:0] I/O I Description During powerup and initialization, M0--M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled. Special-Purpose Pins (Can also be used as a general I/O.) I/O After configuration, these pins are user-programmable I/O.* PLL_CK[0:7] I/O Dedicated PCM clock pins. These pins are a user-programmable I/O pins if not used by PLLs. P[TBTR]CLK[1:0][ I/O Pins dedicated for the primary clock. Input pins on the middle of each side with differential TC] pairing. They may be used as general I/O pins if not needed for clocking purposes. TDI, TCK, TMS I If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary scan is not selected, all boundary scan functions are inhibited once configuration is complete. Even if boundary scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration. I/O After configuration, these pins are user-programmable I/O.* RDY/BUSY/RCLK O During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.* I/O During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. HDC O High during configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* LDC O Low during configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low, open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. After configuration, this pin is a user-programmable I/O pin.* I CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into a status output. As a status indication, a high indicates ready, and a low indicates busy. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe. CS0, CS1 I/O After configuration, these pins are user-programmable I/O pins.* RD/MPI_STRB I I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.* * The FPGA States of Operation section contains more information on how to control these signals during start up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. 64 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 29. FPGA Common-Function Pin Description (continued) Symbol I/O Description A[0:17] I During MPI mode, the A[0:17] are used as the address bus driven by the PowerPC bus master, utilizing the least significant bits of the PowerPC 32-bit address. MPI_BURST MPI_BDIP MPI_TSZ[1:0] MPI_ACK MPI_CLK O During master parallel configuration mode, A[0:17] address the configuration EPROM. In MPI mode, many of the A[n] pins have alternate uses as described below. See the special function blocks section for more MPI information. During configuration, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled. It is driven low to indicate a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. It is driven by the PowerPC processor assertion of this pin indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_TSZ[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. Set 10 for byte, 01 for half-word, and 00 for word. If not used for MPI, these pins are user-programmable I/O pins.* O In PowerPC mode MPI operation, this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle. I This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the embedded system bus. If MPI is used, this can be the AMBA bus clock. MPI_TEA MPI_RTRY D[0:31] O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. O This pin requests that the MPC860 relinquish the bus and retry the cycle. I/O Selectable data bus width from 8-, 16-, 32-bit. Driven by the bus master in a write transaction. Driven by MPI in a read transaction. I D[0:7] receive configuration data during master parallel, peripheral, and slave parallel configuration modes and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:3] output internal status for asynchronous peripheral mode when RD is low. After configuration, the pins are user-programmable I/O pins.* DP[3:0] I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for D[16:23], and DP[3] for D[24:32]. After configuration, this pin is a user-programmable I/O pin.* I During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled. DIN I/O After configuration, this pin is a user-programmable I/O pin.* DOUT O During configuration, DOUT is the serial data output that can drive the DIN of daisychained slave devices. Data out on DOUT changes on the rising edge of CCLK. I/O After configuration, DOUT is a user-programmable I/O pin.* * The FPGA States of Operation section contains more information on how to control these signals during start up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. Agere Systems Inc. 65 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary. Table 30. FPSC Function Pin Description Symbol HSI LVDS Receive Pins rxd_b_p0 rxd_b_n0 rxd_c_p0 rxd_c_n0 rxd_b_p1 rxd_b_n1 rxd_c_p1 rxd_c_n1 rxd_b_p2 rxd_b_n2 rxd_c_p2 rxd_c_n2 rxd_b_p3 rxd_b_n3 rxd_c_p3 rxd_c_n3 rxd_b_p4 rxd_b_n4 rxd_c_p4 rxd_c_n4 rxd_b_p5 rxd_b_n5 rxd_c_p5 rxd_c_n5 rxd_b_p6 rxd_b_n6 rxd_c_p6 rxd_c_n6 rxd_b_p7 rxd_b_n7 rxd_c_p7 rxd_c_n7 DAUTREC VDDA_STM VSSA_STM* I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I LVDS work link--channel AA (shared with RapidIO port B) . LVDS work link--channel AA (shared with RapidIO port B). LVDS protect link--channel AA (shared with RapidIO port C). LVDS protect link--channel AA (shared with RapidIO port C). LVDS work link--channel AB (shared with RapidIO port B). LVDS work link--channel AB (shared with RapidIO port B). LVDS protect link--channel AB (shared with RapidIO port C). LVDS protect link--channel AB (shared with RapidIO port C). LVDS work link--channel AC (shared with RapidIO port B). LVDS work link--channel AC (shared with RapidIO port B). LVDS protect link--channel AC (shared with RapidIO port C). LVDS protect link--channel AC (shared with RapidIO port C). LVDS work link--channel AD (shared with RapidIO port B). LVDS work link--channel AD (shared with RapidIO port B). LVDS protect link--channel AD (shared with RapidIO port C). LVDS protect link--channel AD (shared with RapidIO port C). LVDS work link--channel BA (shared with RapidIO port B). LVDS work link--channel BA (shared with RapidIO port B). LVDS protect link--channel BA (shared with RapidIO port C). LVDS protect link--channel BA (shared with RapidIO port C). LVDS work link--channel BB (shared with RapidIO port B). LVDS work link--channel BB (shared with RapidIO port B). LVDS protect link--channel BB (shared with RapidIO port C). LVDS protect link--channel BB (shared with RapidIO port C). LVDS work link--channel BC (shared with RapidIO port B). LVDS work link--channel BC (shared with RapidIO port B). LVDS protect link--channel BC (shared with RapidIO port C). LVDS protect link--channel BC (shared with RapidIO port C). LVDS work link--channel BD (shared with RapidIO port B). LVDS work link--channel BD (shared with RapidIO port B). LVDS protect link--channel BD (shared with RapidIO port C). LVDS protect link--channel BD (shared with RapidIO port C). Disable auto recovery for the PLL. Internal pull-down. Analog VDD 1.5 V power supply for the HSI block. Analog VSS for the HSI block. I/O Description * The VSSA_STM is combimed with VSS in packages that contain an internal VSS plane. 66 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 30. FPSC Function Pin Description (continued) Symbol HSI LVDS Transmit Pins txd_b_p0 txd_b_n0 txd_c_p0 txd_c_n0 txd_b_p1 txd_b_n1 txd_c_p1 txd_c_n1 txd_b_p2 txd_b_n2 txd_c_p2 txd_c_n2 txd_b_p3 txd_b_n3 txd_c_p3 txd_c_n3 txd_b_p4 txd_b_n4 txd_c_p4 txd_c_n4 txd_b_p5 txd_b_n5 txd_c_p5 txd_c_n5 txd_b_p6 txd_b_n6 txd_c_p6 txd_c_n6 txd_b_p7 txd_b_n7 txd_c_p7 txd_c_n7 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I LVDS work link--channel AA (shared with RapidIO port B). LVDS work link--channel AA (shared with RapidIO port B). LVDS protect link--channel AA (shared with RapidIO port C). LVDS protect link--channel AA (shared with RapidIO port C). LVDS work link--channel AB (shared with RapidIO port B). LVDS work link--channel AB (shared with RapidIO port B). LVDS protect link--channel AB (shared with RapidIO port C). LVDS protect link--channel AB (shared with RapidIO port C). LVDS work link--channel AC (shared with RapidIO port B). LVDS work link--channel AC (shared with RapidIO port B). LVDS protect link--channel AC (shared with RapidIO port C). LVDS protect link--channel AC (shared with RapidIO port C). LVDS work link--channel AD (shared with RapidIO port B). LVDS work link--channel AD (shared with RapidIO port B). LVDS protect link--channel AD (shared with RapidIO port C). LVDS protect link--channel AD (shared with RapidIO port C). LVDS work link--channel BA (shared with RapidIO port B). LVDS work link--channel BA (shared with RapidIO port B). LVDS protect link--channel BA (shared with RapidIO port C). LVDS protect link--channel BA (shared with RapidIO port C). LVDS work link--channel BB (shared with RapidIO port B). LVDS work link--channel BB (shared with RapidIO port B). LVDS protect link--channel BB (shared with RapidIO port C). LVDS protect link--channel BB (shared with RapidIO port C). LVDS work link--channel BC (shared with RapidIO port B). LVDS work link--channel BC (shared with RapidIO port B). LVDS protect link--channel BC (shared with RapidIO port C). LVDS protect link--channel BC (shared with RapidIO port C). LVDS work link--channel BD (shared with RapidIO port B). LVDS work link--channel BD (shared with RapidIO port B). LVDS protect link--channel BD (shared with RapidIO port C). LVDS protect link--channel BD (shared with RapidIO port C). I/O Description Agere Systems Inc. 67 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 30. FPSC Function Pin Description (continued) Symbol HSI Test Signals tstclk mreset testrst resettx tstMUX[9:0]s scan_tstmd scan_en tstsuftld e_toggle elsel exdnup rxd_a_p<7:0> rxd_a_n<7:0> rxsoc_a_p rxsoc_a_n rxclk_a_p rxclk_a_n lvctap_a<1:0> rxd_b_p<7:0> rxd_b_n<7:0> rxsoc_b_p rxsoc_b_n rxclk_b_p rxclk_b_n lvctap_b<4:0> rxd_c_p<7:0> rxd_c_n<7:0> rxsoc_c_p rxsoc_c_n rxclk_c_p rxclk_c_n lvctap_c<4:0> ref10 ref14 reshi reslo VDDA_shim VSSA_shim 68 I I I I O I I I I I I I I I I I I -- I I I I I I -- I I I I I I -- -- -- -- -- I I Test clock for emulation of 622 MHz clock during PLL bypass. Internal pull-down. Test mode reset. Internal pull-down. Resets receiver clock division counter. Internal pull-up. Resets transmitter clock division counter. Internal pull-up. Test mode output port. Test mode enable. Must be tie-low for normal operation. Scan test enable. Internal pull-up. Internal pull-down. Internal pull-down. Internal pull-down. Internal pull-down. LVDS data for RapidIO, receiver port A. LVDS data for RapidIO, receiver port A. LVDS start-of-cell for RapidIO, receiver port A. LVDS start-of-cell for RapidIO, receiver port A. LVDS receive clock for RapidIO, receiver port A. LVDS receive clock for RapidIO, receiver port A. LVDS input center tap (use 0.01 uF to GND) internal pull-up. LVDS data for RapidIO, receiver port B. LVDS data for RapidIO, receiver port B. LVDS start-of-cell for RapidIO, receiver port B. LVDS start-of-cell for RapidIO, receiver port B. LVDS receive clock for RapidIO, receiver port B. LVDS receive clock for RapidIO, receiver port B. LVDS input center tap (use 0.01 F to GND) internal pull-up. LVDS data for RapidIO, receiver port C. LVDS data for RapidIO, receiver port C. LVDS start-of-cell for RapidIO, receiver port C. LVDS start-of-cell for RapidIO, receiver port C. LVDS receive clock for RapidIO, receiver port C. LVDS receive clock for RapidIO, receiver port C. LVDS input center tap (use 0.01 F to GND) internal pull-up. LVDS reference voltage: 1.0 V 3%. LVDS reference voltage: 1.4 V 3%. LVDS resistor high pin ( 100 in series with reslo). LVDS resistor low pin ( 100 in series with reshi). Analog VDD 1.5 V power supply for the Rapid IO block. Analog VSS for the Rapid IO block. Agere Systems Inc. I/O Description RapidIO LVDS Interface Pins (Receiver) * The VSSA_shim is combimed with VSS in packages that contain an internal VSS plane. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 30. FPSC Function Pin Description (continued) Symbol I/O Description RapidIO LVDS Interface Pins (Transmitter) txd_a_p<7:0> txd_a_n<7:0> txsoc_a_p txsoc_a_n txclk_a_p txclk_a_n txd_b_p<7:0> txd_b_n<7:0> txsoc_b_p txsoc_b_n txclk_b_p txclk_b_n txd_c_p<7:0> txd_c_n<7:0> txsoc_c_p txsoc_c_n txclk_c_p txclk_c_n MISC System Signals rst_n I Reset the core only. The FPGA logic is not reset by rst_n. Internal pull down allows chip to stay in reset state when external driver loses power. LVDS system clock, 50% duty cycle, also the reference clock of PLL. LVDS system clock, 50% duty cycle, also the reference clock of PLL. LVDS clock for RapidIO PLL internal pull-up. LVDS clock for RapidIO PLL internal pull-up. Temperature-sensing diode (anode +). Temperature-sensing diode (cathode -). LVDS center-tap for sys_clk (use 0.01 f to GND). LVDS center-tap for gclk (use 0.01 f to GND). O O O O O O O O O O O O O O O O O O LVDS data for RapidIO, transmitter port A. LVDS data for RapidIO, transmitter port A. LVDS start-of-cell for RapidIO, transmitter port A. LVDS start-of-cell for RapidIO, transmitter port A. LVDS receive clock for RapidIO, transmitter port A. LVDS receive clock for RapidIO, transmitter port A. LVDS data for RapidIO, transmitter port B. LVDS data for RapidIO, transmitter port B. LVDS start-of-cell for RapidIO, transmitter port B. LVDS start-of-cell for RapidIO, transmitter port B. LVDS receive clock for RapidIO, transmitter port B. LVDS receive clock for RapidIO, transmitter port B. LVDS data for RapidIO, transmitter port C. LVDS data for RapidIO, transmitter port C. LVDS start-of-cell for RapidIO, transmitter port C. LVDS start-of-cell for RapidIO, transmitter port C. LVDS receive clock for RapidIO, transmitter port C. LVDS receive clock for RapidIO, transmitter port C. sys_clk_p sys_clk_n gclk_p gclk_n dxp dxn lvctap_sk lvctap_gk I I I I -- -- O O Agere Systems Inc. 69 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) In Table 31, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core. Table 31. Embedded Core/FPGA Interface Signal Description Pin Name STM or 8B/10B Signals dinaa<7:0> dinaa_par dinaa_fp dinab<7:0> dinab_par dinab_fp dinac<7:0> dinac_par dinac_fp dinad<7:0> dinad_par dinad_fp dinba<7:0> dinba_par dinba_fp dinbb<7:0> dinbb_par dinbb_fp dinbc<7:0> dinbc_par dinbc_fp dinbd<7:0> dinbd_par dinbd_fp doutaa<7:0> doutaa_par doutaa_spe doutaa_c1j1 doutaa_en doutaa_fp doutab<7:0> doutab_par doutab_spe doutab_c1j1 doutab_en doutab_fp 70 I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O Parallel bus of STM slice A, transmitter A. MSB is bit 7. Parity for STM slice A, transmitter A. Frame pulse or K control for STM slice A, transmitter A. Parallel bus of STM slice A, transmitter B. MSB is bit 7. Parity for STM slice A, transmitter B. Frame pulse or K control for STM slice A, transmitter B. Parallel bus of STM slice A, transmitter C. MSB is bit 7. Parity for STM slice A, transmitter C. Frame pulse or K control for STM slice A, transmitter C. Parallel bus of STM slice A, transmitter D. MSB is bit 7. Parity for STM slice A, transmitter D. Frame pulse or K control for STM slice A, transmitter D. Parallel bus of STM slice B, transmitter A. MSB is bit 7. Parity for STM slice B, transmitter A. Frame pulse or K control for STM slice B, transmitter A. Parallel bus of STM slice B, transmitter B. MSB is bit 7. Parity for STM slice B, transmitter B. Frame pulse or K control for STM slice B, transmitter B. Parallel bus of STM slice B, transmitter C. MSB is bit 7. Parity for STM slice B, transmitter C. Frame pulse or K control for STM slice B, transmitter C. Parallel bus of STM slice B, transmitter D. MSB is bit 7. Parity for STM slice B, transmitter D. Frame pulse or K control for STM slice B, transmitter D. Parallel bus of STM slice A, receiver A. MSB is bit 7. Parity for parallel bus of STM slice A, receiver A. SPE signal for parallel bus of STM slice A, receiver A. C1J1 signal for parallel bus of STM slice A, receiver A. Enable for parallel bus of STM slice A, receiver A. Frame pulse or COMMADET for parallel bus of STM slice A, receiver A. Parallel bus of STM slice A, receiver B. MSB is bit 7. Parity for parallel bus of STM slice A, receiver B. SPE signal for parallel bus of STM slice A, receiver B. C1J1 signal for parallel bus of STM slice A, receiver B. Enable for parallel bus of STM slice A, receiver B. Frame pulse or COMMADET for parallel bus of STM slice A, receiver B. Agere Systems Inc. I/O Description Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name I/O Description STM or 8B/10B Signals (continued) doutac<7:0> doutac_par doutac_spe doutac_c1j1 doutac_en doutac_fp doutad<7:0> doutad_par doutad_spe doutad_c1j1 doutad_en doutad_fp doutba<7:0> doutba_par doutba_spe doutba_c1j1 doutba_en doutba_fp doutbb<7:0> doutbb_par doutbb_spe doutbb_c1j1 doutbb_en doutbb_fp doutbc<7:0> doutbc_par doutbc_spe doutbc_c1j1 doutbc_en doutbc_fp doutbd<7:0> doutbd_par doutbd_spe doutbd_c1j1 doutbd_en doutbd_fp O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Parallel bus of STM slice A, receiver C. MSB is bit 7. Parity for parallel bus of STM slice A, receiver C. SPE signal for parallel bus of STM slice A, receiver C. C1J1 signal for parallel bus of STM slice A, receiver C. Enable for parallel bus of STM slice A, receiver C. Frame pulse or COMMADET for parallel bus of STM slice A, receiver C. Parallel bus of STM slice A, receiver D. MSB is bit 7. Parity for parallel bus of STM slice A, receiver D. SPE signal for parallel bus of STM slice A, receiver D. C1J1 signal for parallel bus of STM slice A, receiver D. Enable for parallel bus of STM slice A, receiver D. Frame pulse or COMMADET for parallel bus of STM slice A, receiver D. Parallel bus of STM slice B, receiver A. MSB is bit 7. Parity for parallel bus of STM slice B, receiver A. SPE signal for parallel bus of STM slice B, receiver A. C1J1 signal for parallel bus of STM slice B, receiver A. Enable for parallel bus of STM slice B, receiver A. Frame pulse or COMMADET for parallel bus of STM slice B, receiver A. Parallel bus of STM slice B, receiver B. MSB is bit 7. Parity for parallel bus of STM slice B, receiver B. SPE signal for parallel bus of STM slice B, receiver B. C1J1 signal for parallel bus of STM slice B, receiver B. Enable for parallel bus of STM slice B, receiver B. Frame pulse or COMMADET for parallel bus of STM slice B, receiver B. Parallel bus of STM slice B, receiver C. MSB is bit 7. Parity for parallel bus of STM slice B, receiver C. SPE signal for parallel bus of STM slice B, receiver C. C1J1 signal for parallel bus of STM slice B, receiver C. Enable for parallel bus of STM slice B, receiver C. Frame pulse or COMMADET for parallel bus of STM slice B, receiver C. Parallel bus of STM slice B, receiver D. MSB is bit 7. Parity for parallel bus of STM slice B, receiver D. SPE signal for parallel bus of STM slice B, receiver D. C1J1 signal for parallel bus of STM slice B, receiver D. Enable for parallel bus of STM slice B, receiver D. Frame pulse or COMMADET for parallel bus of STM slice B, receiver D. Agere Systems Inc. 71 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name TOH Signals toh_clk toh_inaa toh_inab toh_inac toh_inad toh_inba toh_inbb toh_inbc toh_inbd tx_toh_ck_en toh_outaa toh_outab toh_outac toh_outad toh_outba toh_outbb toh_outbc toh_outbd rx_toh_ck_en rx_toh_fp toh_ck_fp_en toh_aa_en toh_ab_en toh_ac_en toh_ad_en toh_ba_en toh_bb_en toh_bc_en toh_bd_en I I I I I I I I I I O O O O O O O O O O O O O O O O O O O TX and RX TOH serial links clock (25 MHz to 77.76 MHz). TOH serial link for STM slice A, transmitter A. TOH serial link for STM slice A, transmitter B. TOH serial link for STM slice A, transmitter C. TOH serial link for STM slice A, transmitter D. TOH serial link for STM slice B, transmitter A. TOH serial link for STM slice B, transmitter B. TOH serial link for STM slice B, transmitter C. TOH serial link for STM slice B, transmitter D. TX TOH serial link clock enable. TOH serial link for STM slice A, receiver A. TOH serial link for STM slice A, receiver B. TOH serial link for STM slice A, receiver C. TOH serial link for STM slice A, receiver D. TOH serial link for STM slice B, receiver A. TOH serial link for STM slice B, receiver B. TOH serial link for STM slice B, receiver C. TOH serial link for STM slice B, receiver D. RX TOH serial link clock enable. RX TOH serial link frame pulse. A soft register bit available to enable RX TOH clock and frame pulse. RX TOH enable, soft register. AND output of resistor channel AA enable and hi-z control of TOH data output AA. RX TOH enable, soft register. AND output of resistor channel AB enable and hi-z control of TOH data output AB. RX TOH enable, soft register. AND output of resistor channel AC enable and hi-z control of TOH data output AC. RX TOH enable, soft register. AND output of resistor channel AD enable and hi-z control of TOH data output AD. RX TOH enable, soft register. AND output of resistor channel BA enable and hi-z control of TOH data output BA. RX TOH enable, soft register. AND output of resistor channel BB enable and hi-z control of TOH data output BB. RX TOH enable, soft register. AND output of resistor channel BC enable and hi-z control of TOH data output BC. RX TOH enable, soft register. AND output of resistor channel BD enable and hi-z control of TOH data output BD. I/O Description 72 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name I/O Description STM Clock and Control sys_fp line_fp fpga_sysclk prot_switch_aa prot_switch_ac prot_switch_ba prot_switch_bc lvds_prot_aa lvds_prot_ab lvds_prot_ac lvds_prot_ad lvds_prot_ba lvds_prot_bb lvds_prot_bc lvds_prot_bd core_ready I I O I I I I I I I I I I I I O System frame pulse for transmitter section. Line frame pulse for receiver section. System clock (sys_clk). This signal is routed onto a primary clock net inside the FPGA, with very low skew. STM channel protection enable for channels aa and ab. Active-high. STM channel protection enable for channels ac and ac. Active-high. STM channel protection enable for channels ba and bb. Active-high. STM channel protection enable for channels bc and bd. Active-high. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. LVDS buffer redundancy select for rx channel aa. Active-high for redundant link. During powerup and FPGA configuration sequence, the core_ready is held low. At the end of FPGA configuration, the core_ready will be held low for six clock (sys_clk) cycles and then go active-high. Flag indicates that the embedded core is out of its reset state. Recovered clock for STM slice A, channel A. Recovered clock for STM slice A, channel B. Recovered clock for STM slice A, channel C. Recovered clock for STM slice A, channel D. Recovered clock for STM slice B, channel A. Recovered clock for STM slice B, channel B. Recovered clock for STM slice B, channel C. Recovered clock for STM slice B, channel D. K control bit for channel AA. K control bit for channel AB. K control bit for channel AC. K control bit for channel AD. K control bit for channel BA. K control bit for channel BB. K control bit for channel BC. K control bit for channel BD. cdr_clk_aa cdr_clk_ab cdr_clk_ac cdr_clk_ad cdr_clk_ba cdr_clk_bb cdr_clk_bc cdr_clk_bd 8B/10B Mode Signals tx_k_ctrl_aa tx_k_ctrl_ab tx_k_ctrl_ac tx_k_ctrl_ad tx_k_ctrl_ba tx_k_ctrl_bb tx_k_ctrl_bc tx_k_ctrl_bd O O O O O O O O I I I I I I I I Agere Systems Inc. 73 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name RapidIO Signals (Channel A) csysenb_a O System cell processing enable. After reset is released, drive this signal high when RapidIO is ready to transmit cells. This signal should be active after all control signals into the RapidIO are stable. Synchronous reset for all memory elements clocked by WRXCLK_A_FPGA (derived from PLL). Transmit data bus containing four octets synchronized with the rising edge of the 60 MHz--146 MHz WUTXCLK_FPGA (derived from PLL) is clocked into the transmit FIFO within the RapidIO. Start of cell originating with the core and synchronized with the rising edge of WUTXCLK_FPGA into the transmit FIFO. Indicates that the first data word on TXD_A bus includes the first octet of a new cell in bit positions <31:24>. Synchronous reset for all memory elements in the WUTXCLK_FPGA domain. Output 3-state enable (active-low). When active, the TXD_A, TXSOC_A, and TXCLK_A LVDS drivers are 3-stated. 3-state override for transmit outputs (active-low). This signal is ignored during reset, but takes priority over all 3-state control signals otherwise. 32-bit data from the receive module. The bus contains four octets and reflects data received via the high-speed RXD_A data bus. Indicates the presence of the first octet of a new cell within the first 32-bit data word on the RXD_A bus in bit positions <31:24>. Indicates a minimum cell violation within the receive module. This signal will transition active-high coincident with RXSOC. This indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. Indicates an alignment error. An active state signals RXSOC was captured on a negative RXCLK edge. This signal will stay high for a single WRXCLK_A_FPGA cycle coincident with RXSOC. Indicates the loss or absence of a clock on the LVDS clock (RXCLK). After the validation of the absence of the clock, this signal will stay high for the duration of the absence of the clock. Derived from high-speed LVDS clock RXCLK (= RXCLK/2). System cell processing enable. After reset is released, drive this signal high when RapidIO is ready to transmit cells. This signal should be active after all control signals into the RapidIO are stable. Agere Systems Inc. I/O Description rstn_rx_a utxd_a<31:0> O O utxsoc_a O rstn_utx_a utxtristn_a ytristn_a O O O zrxd_a<31:0> O zrxsoc_a O zrxsocviol_a O zrxalnviol_a O zclkstat_a O wrxclk_a_fpga RapidIO Signals (Channel B) csysenb_b O I 74 Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name I/O Description RapidIO Signals (Channel B) (continued) rstn_rx_b utxd_b<31:0> I I Synchronous reset for all memory elements clocked by WRXCLK_B_FPGA (derived from PLL). Transmit data bus containing four octets synchronized with the rising edge of the 60 MHz--146 MHz WUTXCLK_FPGA (derived from PLL) is clocked into the transmit FIFO within the RapidIO. Start of cell originating with the core and synchronized with the rising edge of WUTXCLK_FPGA into the transmit FIFO. Indicates that the first data word on TXD_B bus includes the first octet of a new cell in bit positions <31:24>. Synchronous reset for all memory elements in the WUTXCLK_FPGA domain. Output 3-state enable (active-low). When active, the TXD_B, TXSOC_B, and TXCLK_B LVDS drivers are 3-stated. 3-state override for transmit outputs (active-low). This signal is ignored during reset, but takes priority over all 3-state control signals otherwise. 32-bit data from the receive module. The bus contains four octets and reflects data received via the high-speed RXD_B data bus. Indicates the presence of the first octet of a new cell within the first 32-bit data word on the RXD_B bus in bit positions <31:24>. Indicates a minimum cell violation within the receive module. This signal will transition active-high coincident with RXSOC. This indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. Indicates an alignment error. An active state signals RXSOC was captured on a negative RXCLK edge. This signal will stay high for a single WRXCLK_B_FPGA cycle coincident with RXSOC. Indicates the loss or absence of a clock on the LVDS clock (RXCLK). After the validation of the absence of the clock, this signal will stay high for the duration of the absence of the clock. Derived from high-speed LVDS clock RXCLK (= RXCLK/2). System cell processing enable. After reset is released, drive this signal high when RapidIO is ready to transmit cells. This signal should be active after all control signals into the RapidIO are stable. Synchronous reset for all memory elements clocked by WRXCLK_C_FPGA (derived from PLL). utxsoc_b I rstn_utx_b utxtristn_b ytristn_b I I I zrxd_b<31:0> O zrxsoc_b O zrxsocviol_b O zrxalnviol_b O zclkstat_b O wrxclk_b_fpga RapidIO Signals (Channel C) csysenb_c O I rstn_rx_c I Agere Systems Inc. 75 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name I/O Description RapidIO Signals (Channel C) (continued) utxd_c<31:0> I Transmit data bus containing four octets synchronized with the rising edge of the 60 MHz--146 MHz WUTXCLK_FPGA (derived from PLL) is clocked into the transmit FIFO within the RapidIO. Start of cell originating with the core and synchronized with the rising edge of WUTXCLK_FPGA into the transmit FIFO. Indicates that the first data word on TXD_C bus includes the first octet of a new cell in bit positions <31:24>. Synchronous reset for all memory elements in the WUTXCLK_FPGA domain. Output 3-state enable (active-low). When active, the TXD_C, TXSOC_C, and TXCLK_C LVDS drivers are 3-stated. 3-state override for transmit outputs (active-low). This signal is ignored during reset, but takes priority over all 3-state control signals otherwise. 32-bit data from the receive module. The bus contains four octets and reflects data received via the high-speed RXD_C data bus. Indicates the presence of the first octet of a new cell within the first 32-bit data word on the RXD_C bus in bit positions <31:24>. Indicates a minimum cell violation within the receive module. This signal will transition active-high coincident with RXSOC. This indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. Indicates an alignment error. An active state signals RXSOC was captured on a negative RXCLK edge. This signal will stay high for a single WRXCLK_C_FPGA cycle coincident with RXSOC. Indicates the loss or absence of a clock on the LVDS clock (RXCLK). After the validation of the absence of the clock, this signal will stay high for the duration of the absence of the clock. Derived from high-speed LVDS clock RXCLK (= RXCLK/2). One X core clock (60 MHz--146 MHz) generated from an internal PLL circuit. Input data on UTXD<31:0> and UTXSCO are synchronous to this clock. The transmit FIFO inputs are clocked by this clock. The test interface module also runs off this clock. This clock is sent to the FPGA logic. 1/2 X main PLL output clock. Phase aligned with PFCLK. Nominal frequency range is 30 MHz to 73 MHz. Duty cycle spec is 47%/53%. utxsoc_c I rstn_utx_c utxtristn_c ytristn_c I I I zrxd_c<31:0> O zrxsoc_c O zrxsocviol_c O zrxalnviol_c O zclkstat_c O wrxclk_c_fpga RapidIO Signals wutxclk_fpga O O halfclk_fpga O 76 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver current design, but does not necessarily guard against issues that can occur when design changes are made that affect I/O registers. -- 2X/4X I/O Shift Registers. If 2X I/O shift registers or 4X I/O shift registers are used in the design, this may cause incompatibilities between the ORT880L and ORT8850H because only the A and C I/Os in a PIC support 2X I/O shift registers and only A I/Os supports 4X I/O shift register mode. A and C I/Os are shown in the following pinout tables under the I/O pad columns as those ending in A or C. s Pin Information (continued) Package Pinouts Table 33 and Table 34 provide the package pin and pin function for the ORT8850 FPSC and packages. The bond pad name is identified in the PIO nomeclature used in the ORCA Foundry design editor. The Bank column provides information as to which output voltage level bank the given pin is in. The Group column provides information as to the group of pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-ended limitedswing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then the VREF pin is available as an I/O pin. When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for the FPGA. The tables provide no information on unused pads. The pinouts for both the ORT8850H and ORT8850L in the 680 PBGAM package are shown in Table 32. In order to allow pin-for-pin compatible board layouts that can accommodate both devices, some key compatibility issues include the following.: s Edge Clock Input Pins. The input buffers for fast edge clocks are only available at the C I/O pad. The C I/Os are shown in the following pinout tables under the I/O pad colums as those ending in C. Unused Pins. One of the incompatibilities is due to the fact that the ORT8850L is a much smaller array and does not provide as many programmable IOs (PIOs). Table 32 shows a list of bonded ORT8850H PIOs that are unused in the ORT8850L. s Table 32. ORT8850H Pins That Are Unused in ORT8850L BGA Ball Bonds K4 M5 R5 T5 W4 AA2 Y4 AC4 AD5 AG1 AP4 AK10 AK11 AM9 AN9 AM14 AN14 D11 E13 ORT8850H PIOs PL11A PL13A PL20A PL21A PL27A PL28A PL29A PL35A PL37A PL38A PB3A PB9A PB10A PB11A PB12A PB19A PB20A PT12A PT11A Unused Pins. As shown in Table 32, there are 19 balls that are not available in the ORT8850L, but are available in the ORT8850H. These user I/Os should not be used if the ORT8850L may be used. Shared Control Signals on I/O Registers. The ORCA Series 4 architecture shares clock and control signals between two adjacent I/O pads. If I/O registers are used, incompatibilities may arise between ORT8850L and ORT8850H when different clock or control signals are needed on adjacent package pins. This is because one device may allow independent clock or control signals on these adjacent pins, while the other may force them to be the same. There are two ways to avoid this issue. -- Always keep an open bonded pin (non-bonded pins for the ORT8850L do not count) between pins that require different clock or control signals. Note that this open pin can be used to connect signals that do not require the use of I/O registers to meet timing. -- Place and route the design in both the ORT8850H and ORT8850L to verify both produce valid designs. Note that this method guarantees the s Users should avoid using these pins if they plan to migrate their ORT8850H design to an ORT8850L. Agere Systems Inc. 77 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout BA352 A1 B1 C2 AA23 C1 E4 D1 D2 E3 E2 A2 E1 F3 F2 G4 G3 A26 G2 F1 H2 H3 G1 H1 AC13 J4 J3 AA4 J2 J1 K4 K3 K2 K1 AD3 L1 L2 L3 M1 M2 AE1 M4 M3 78 VDDIO Bank -- -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) VREF Group -- -- -- -- -- -- -- -- 7 7 -- 7 7 7 8 8 -- 9 -- 9 9 9 9 -- 10 10 -- 10 10 1 1 1 1 -- 2 2 -- 2 2 -- 3 3 I/O VSS VDD33 O VDD15 I I I VDDIO0 IO IO VSS IO IO IO IO IO VSS IO VDDIO0 IO IO IO IO VSS IO IO VDD15 IO IO IO IO IO IO VSS IO IO VDDIO7 IO IO VSS IO IO ORT8850L VSS VDD33 PRD_DATA VDD15 PRESET_N PRD_CFG_N PPRGRM_N VDDIO0 PL2D PL2C VSS PL2A PL3D PL3C PL4D PL4C VSS PL5C VDDIO0 PL5B PL5A PL6D PL6C VSS PL7D PL7C VDD15 PL7B PL7A PL8D PL8C PL9D PL9C VSS PL10D PL10C VDDIO7 PL10B PL10A VSS PL11B PL11A Additional Function -- -- RD_DATA/TDO -- RESET_N RD_CFG_N PRGRM_N -- PLL_CK0C/HPPLL PLL_CK0T/HPPLL -- VREF_0_07 D5 D6 HDC LDC_N -- D7 -- VREF_0_09 A17/PPC_A31 CS0_N CS1 -- INIT_N DOUT -- VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 VREF_7_01 D4 -- RDY/BUSY_N/RCLK VREF_7_02 -- A13/PPC_A27 A12/PPC_A26 -- A11/PPC_A25 VREF_7_03 Pair -- -- -- -- -- -- -- -- L12C_A0 L12T_A0 -- -- L13C_A0 L13T_A0 L14C_A0 L14T_A0 -- -- -- L15C_A0 L15T_A0 L16C_A0 L16T_A0 -- L17C_A0 L17T_A0 -- L18C_A0 L18T_A0 L1C_A0 L1T_A0 L2C_A0 L2T_A0 -- L3C_A0 L3T_A0 -- L4C_A0 L4T_A0 -- L5C_A0 L5T_A0 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 AC11 N2 N3 AE2 N1 P1 P2 AE25 P3 P4 AF1 R1 R2 AC16 R3 R4 AF25 T1 T2 U1 U2 T3 V1 V2 W1 Y1 U3 U4 V3 W2 Y2 W3 AA1 AB1 B25 W4 Y3 Y4 AA2 AA3 B26 AB3 VDDIO Bank -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) VREF Group -- 4 4 -- 4 4 -- -- 5 5 -- 5 5 -- 6 6 -- 6 6 6 6 -- 7 7 8 8 8 8 8 8 8 8 1 1 -- 1 1 -- 3 3 -- 3 I/O VDD15 IO IO VSS IO IO VDDIO7 VSS IO IO VSS IO IO VDD15 IO IO VSS IO IO IO IO VDDIO7 IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO VDDIO6 IO IO VSS IO ORT8850L VDD15 PL13D PL13C VSS PL14D PL14C VDDIO7 VSS PL15D PL15C VSS PL16D PL16C VDD15 PL17D PL17C VSS PL17B PL17A PL18D PL18C VDDIO7 PL19D PL19C PL20D PL20C PL20B PL20A PL21D PL21C PL21B PL21A PL22D PL22C VSS PL22B PL22A VDDIO6 PL24D PL24C VSS PL25D Additional Function -- RD_N/MPI_STRB_N VREF_7_04 -- PLCK0C PLCK0T -- -- A10/PPC_A24 A9/PPC_A23 -- A8/PPC_A22 VREF_7_05 -- PLCK1C PLCK1T -- VREF_7_06 A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 -- WR_N/MPI_RW VREF_7_07 A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 -- D9 D10 -- D11 D12 -- VREF_6_03 Pair -- L6C_A0 L6T_A0 -- L7C_A0 L7T_A0 -- -- L8C_A0 L8T_A0 -- L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 -- L11C_A0 L11T_A0 L12C_A0 L12T_A0 -- L13C_A0 L13T_A0 L14C_A0 L14T_A0 L15C_A0 L15T_A0 L16C_D0 L16T_D0 L17C_D0 L17T_D0 L1C_A0 L1T_A0 -- L2C_D0 L2T_D0 -- L3C_A0 L3T_A0 -- L4C_A0 79 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 AB2 AC2 C24 AC1 AD1 C3 D14 AB4 AC3 AC21 AD2 AF2 D19 AE3 AC6 AF3 AD4 AE4 AC5 AD5 D23 AE5 AF4 AC7 AD6 AE6 AF5 AF6 D4 AD7 AE7 AD8 AE8 AF7 AF8 D9 AC9 AD9 AE9 AF9 AC10 AD10 80 VDDIO Bank 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) -- -- -- 6 (BL) -- -- -- -- -- -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) VREF Group 3 4 -- 4 4 -- -- -- -- -- -- -- -- -- -- 5 5 5 5 5 -- 6 6 -- 7 7 7 7 -- 7 7 8 8 8 8 -- 9 9 9 9 10 10 I/O IO IO VSS IO IO VSS VSS I VDDIO6 VDD15 IO VDD33 VSS VDD33 VDD15 IO IO IO IO IO VSS IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO IO IO VSS IO IO IO IO IO IO ORT8850L PL25C PL26C VSS PL27D PL27C VSS VSS PTEMP VDDIO6 VDD15 LVDS_R VDD33 VSS VDD33 VDD15 PB2A PB2C PB2D PB3C PB3D VSS PB4C PB4D VDDIO6 PB5C PB5D PB6A PB6B VSS PB6C PB6D PB7A PB7B PB7C PB7D VSS PB8C PB8D PB9C PB9D PB10C PB10D Additional Function D13 VREF_6_04 -- PLL_CK7C/HPPLL PLL_CK7T/HPPLL -- -- PTEMP -- -- LVDS_R -- -- -- -- DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_6_05 DP3 -- VREF_6_06 D14 -- D15 D16 D17 D18 -- VREF_6_07 D19 D20 D21 VREF_6_08 D22 -- D23 D24 VREF_6_09 D25 D26 D27 Pair L4T_A0 -- -- L5C_A0 L5T_A0 -- -- -- -- -- -- -- -- -- -- -- L6T_A0 L6C_A0 L7T_A0 L7C_A0 -- L8T_D0 L8C_D0 -- L9T_A0 L9C_A0 L10T_A0 L10C_A0 -- L11T_A0 L11C_A0 L12T_A0 L12C_A0 L13T_A0 L13C_A0 -- L14T_A0 L14C_A0 L15T_A0 L15C_A0 L16T_A0 L16C_A0 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 AE10 AD11 AE11 AF10 AF11 AC12 AD12 AE12 AF12 H4 AE13 AF13 AD13 AF14 AE14 D11 AD14 AC14 J23 AF15 AE15 N4 AD15 AC15 P23 AF16 AF17 AE16 AD16 V4 AE17 AD17 W23 AC17 AF18 AF19 L11 AE18 AD18 D16 L12 L13 VDDIO Bank 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- -- -- VREF Group -- 10 10 11 11 11 11 1 1 -- 1 1 -- 2 2 -- 2 2 -- 3 3 -- 3 3 -- 3 3 4 4 -- 4 4 -- -- 5 5 -- 6 6 -- -- -- I/O VDDIO6 IO IO IO IO IO IO IO IO VSS IO IO VDDIO5 IO IO VDD15 IO IO VSS IO IO VSS IO IO VSS IO IO IO IO VSS IO IO VSS VDDIO5 IO IO VSS IO IO VDD15 VSS VSS ORT8850L VDDIO6 PB11C PB11D PB12A PB12B PB12C PB12D PB14A PB14B VSS PB15A PB15B VDDIO5 PB16A PB16B VDD15 PB17A PB17B VSS PB18A PB18B VSS PB19A PB19B VSS PB20A PB20B PB21A PB21B VSS PB22A PB22B VSS VDDIO5 PB23C PB23D VSS PB26A PB26B VDD15 VSS VSS Additional Function -- VREF_6_10 D28 D29 D30 VREF_6_11 D31 -- -- -- VREF_5_01 -- -- PBCK0T PBCK0C -- VREF_5_02 -- -- -- VREF_5_03 -- -- -- -- PBCK1T PBCK1C -- -- -- -- VREF_5_04 -- -- -- VREF_5_05 -- -- VREF_5_06 -- -- -- Pair -- L17T_A0 L17C_A0 L18T_A0 L18C_A0 L19T_A0 L19C_A0 L1T_A0 L1C_A0 -- L2T_A0 L2C_A0 -- L3T_A0 L3C_A0 -- L4T_A0 L4C_A0 -- L5T_A0 L5C_A0 -- L6T_A0 L6C_A0 -- L7T_A0 L7C_A0 L8T_A0 L8C_A0 -- L9T_A0 L9C_A0 -- -- L10T_A0 L10C_A0 -- L11T_A0 L11C_A0 -- -- -- 81 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 AE19 AD19 AC19 AF20 AF21 L14 AE20 AD20 AC20 AE21 AD21 L15 D21 AF22 AF23 AE22 AD22 AC22 L16 M11 M12 AE23 AD23 AF24 AE24 AE26 M13 D6 F23 M14 M15 AB23 AC24 AD25 AD26 M16 AC25 AC26 AB24 AA24 N11 AB25 82 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O O O VDD33 O O VSS O O VDD33 O O VSS VDD15 O O VDD33 O O VSS VSS VSS I I VDD33 I I VSS VDD15 VDD15 VSS VSS VDD33 I I I VSS I I I I VSS I ORT8850L TXD_C0_N TXD_C0_P VDD33 TXD_C1_N TXD_C1_P VSS TXD_C2_N TXD_C2_P VDD33 TXD_C3_N TXD_C3_P VSS VDD15 TXSOC_C_N TXSOC_C_P VDD33 TXCLK_C_N TXCLK_C_P VSS VSS VSS DAUTREC TSTCLK VDD33 TESTRST TSTSHFTLD VSS VDD15 VDD15 VSS VSS VDD33 RESETTX ETOGGLE ECSEL VSS EXDNUP MRESET RXD_C0_N RXD_C0_P VSS RXD_C1_N Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair L1N_A0 L1P_A0 -- L2N_A0 L2P_A0 -- L3N_A0 L3P_A0 -- L4N_A0 L4P_A0 -- -- L5N_A0 L5P_A0 -- L6N_A0 L6P_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L7N_A0 L7P_A0 -- L8N_A0 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 AB26 Y23 Y24 Y25 N12 AA25 AA26 W24 Y26 W26 N13 V23 V24 W25 N14 F4 N15 U24 U23 N16 V25 V26 U25 U26 P11 T24 T25 P12 T26 R26 L23 R23 R24 R25 P13 P26 P25 P24 P14 N26 P15 L4 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O I I I I VSS I I I I I VSS I I I VSS VDD15 VSS VDDA_STM VSSA_STM VSS I I VDD33 I VSS I I VSS I I VDD15 I I I VSS I I I VSS VDD33 VSS VDD15 ORT8850L RXD_C1_P LVCTAP_C_0 RXD_C2_N RXD_C2_P VSS RXD_C3_N RXD_C3_P LVCTAP_C_1 RXSOC_C_N RXSOC_C_P VSS RXCLK_C_N RXCLK_C_P LVCTAP_C_2 VSS VDD15 VSS VDDA_STM VSSA_STM VSS SYS_CLK_N SYS_CLK_P VDD33 LVCTAP_SK VSS RXD_B0_N RXD_B0_P VSS RXD_B1_N RXD_B1_P VDD15 LVCTAP_B_0 RXD_B2_N RXD_B2_P VSS RXD_B3_N RXD_B3_P LVCTAP_B_1 VSS VDD33 VSS VDD15 Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair L8P_A0 -- L9N_A0 L9P_A0 -- L10N_A0 L10P_A0 -- L11N_A0 L11P_A0 -- L12N_A0 L12P_A0 -- -- -- -- -- -- -- L13N_A0 L13P_A0 -- -- -- L14N_A0 L14P_A0 -- L15N_A0 L15P_A0 -- -- L16N_A0 L16P_A0 -- L17N_A0 L17P_A0 -- -- -- -- -- 83 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 P16 R11 N24 N23 N25 M26 M25 R12 M24 M23 L26 K26 R13 L25 L24 K25 K24 R14 J26 J25 H26 G26 K23 J24 F26 H25 G25 H24 H23 E26 E25 G24 G23 F25 F24 D26 C26 D25 E24 C25 E23 D24 84 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VSS VSS I I I I VDD33 VSS O O O O VSS O O O O VSS VDD33 I I VDD33 I VDDA_SHIM VSSA_SHIM I I I I I VDD33 I I I I I VDD33 O O O O O ORT8850L VSS VSS RESLO RESHI REF14 REF10 VDD33 VSS TXD_B0_N TXD_B0_P TXD_B1_N TXD_B1_P VSS TXD_B2_N TXD_B2_P TXD_B3_N TXD_B3_P VSS VDD33 GCLK_N GCLK_P VDD33 LVCTAP_GK VDDA_SHIM VSSA_SHIM RXD_A0_N RXD_A0_P RXD_A1_N RXD_A1_P LVCTAP_A_0 VDD33 RXSOC_A_N RXSOC_A_P RXCLK_A_N RXCLK_A_P LVCTAP_A_2 VDD33 TSTMUX0S TSTMUX1S TSTMUX2S TSTMUX3S TSTMUX4S Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair -- -- -- -- -- -- -- -- L18N_A0 L18P_A0 L19N_A0 L19P_A0 -- L20N_A0 L20P_A0 L21N_A0 L21P_A0 -- -- L22N_D0 L22P_D0 -- -- -- -- L23N_A0 L23P_A0 L24N_A0 L24P_A0 -- -- L25N_A0 L25P_A0 L26N_A0 L26P_A0 -- -- -- -- -- -- -- Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 A25 B24 A24 C23 B23 A23 D22 C22 A22 B22 C21 B21 A21 D20 C20 B20 A20 C19 B19 A19 R15 D18 C18 B18 A18 R16 D17 C17 B17 A17 C16 B16 A16 T11 D15 C15 T23 B15 A15 T12 C14 B14 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 -- 1 1 2 2 -- 2 2 -- 3 3 -- 3 3 -- 4 4 I/O VDD33 O VDD33 O O O O VDD33 I I I O O O O O O O O VDD33 VSS IO IO IO IO VSS IO IO IO IO VDDIO1 IO IO VSS IO IO VDD15 IO IO VSS IO IO ORT8850L VDD33 TSTMUX5S VDD33 TSTMUX6S TSTMUX7S TSTMUX8S TSTMUX9S VDD33 SCANEN SCAN_TSTMD RST_N TXD_A0_N TXD_A0_P TXD_A1_N TXD_A1_P TXSOC_A_N TXSOC_A_P TXCLK_A_N TXCLK_A_P VDD33 VSS PT26D PT26C PT25D PT25C VSS PT25B PT25A PT24D PT24C VDDIO1 PT23D PT23C VSS PT22D PT22C VDD15 PT21D PT21C VSS PT19D PT19C Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_01 -- -- -- -- -- VREF_1_02 -- -- -- -- -- VREF_1_03 -- -- -- -- -- -- Pair -- -- -- -- -- -- -- -- -- -- -- L27N_A0 L27P_A0 L28N_A0 L28P_A0 L29N_A0 L29P_A0 L30N_A0 L30P_A0 -- -- L1C_A0 L1T_A0 L2C_A0 L2T_A0 -- L3C_A0 L3T_A0 L4C_A0 L4T_A0 -- L5C_A0 L5T_A0 -- L6C_A0 L6T_A0 -- L7C_A0 L7T_A0 -- L8C_A0 L8T_A0 85 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 T13 C13 D13 A14 B13 A13 T14 C12 D12 T4 B12 A12 T15 B11 C11 T16 A11 A10 B10 C10 D10 B9 C9 A9 B8 A8 A7 C8 D8 AC18 B7 C7 B6 C6 D7 A6 A5 AC23 B5 C5 A4 AC4 86 VDDIO Bank -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) -- VREF Group -- 4 4 -- 5 5 -- 5 5 -- 5 5 -- 6 6 -- 1 1 -- 1 1 2 2 2 2 2 2 3 3 -- 4 4 4 4 -- 5 5 -- 5 5 6 -- I/O VSS IO IO VDDIO1 IO IO VSS IO IO VDD15 IO IO VSS IO IO VSS IO IO VDDIO0 IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO VSS IO IO IO VSS ORT8850L VSS PT18D PT18C VDDIO1 PT17D PT17C VSS PT16D PT16C VDD15 PT15D PT15C VSS PT13D PT13C VSS PT11D PT11C VDDIO0 PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A PT7D PT7C VSS PT7B PT7A PT6D PT6C VDDIO0 PT5D PT5C VSS PT4D PT4C PT3C VSS Additional Function -- -- VREF_1_04 -- PTCK1C PTCK1T -- PTCK0C PTCK0T -- VREF_1_05 -- -- -- VREF_1_06 -- MPI_RTRY_N MPI_ACK_N -- M0 M1 MPI_CLK A21/MPI_BURST_N M2 M3 VREF_0_02 MPI_TEA_N D0 TMS -- A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 -- D1 D2 -- TDI TCK VREF_0_06 -- Pair -- L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 -- L11C_A0 L11T_A0 -- L12C_A0 L12T_A0 -- L13C_A0 L13T_A0 -- L1C_A0 L1C_A0 -- L2C_A0 L2T_A0 L3C_A0 L3C_A0 L4C_D0 L4T_D0 L5C_A0 L5T_A0 L6C_A0 L6T_A0 -- L7C_A0 L7T_A0 L8C_A0 L8T_A0 -- L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 -- -- Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued) BA352 B4 C4 A3 B3 D3 D5 AC8 AD24 AF26 B2 VDDIO Bank 0 (TL) 0 (TL) -- -- -- -- -- -- -- -- VREF Group 6 6 -- -- -- -- -- -- -- -- I/O IO IO O IO IO VDD33 VSS VSS VSS VSS ORT8850L Additional Function Pair L11C_A0 L11T_A0 -- -- -- -- -- -- -- -- PT2D PLL_CK1C/PPLL PT2C PLL_CK1T/PPLL PCFG_MPI_IRQ CFG_IRQ_N/MPI_IRQ_N PCCLK CCLK PDONE DONE VDD33 -- VSS -- VSS -- VSS -- VSS -- Agere Systems Inc. 87 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout BM680 A1 E4 F5 D2 E3 G5 C4 F4 D1 A2 E2 F3 G4 H5 D3 E1 F2 J5 G3 A18 H4 F1 G2 H3 E5 K5 J4 G1 L5 A33 H2 J3 H1 J2 K3 L4 J1 K2 L1 M4 L3 K1 88 VDDIO VREF Bank Group -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- -- -- -- -- -- -- 7 7 -- 7 7 7 7 -- 8 8 8 8 -- 8 8 9 9 -- 9 9 9 9 -- 10 10 10 10 10 10 1 1 -- 1 1 1 I/O VSS VDD33 O I I I VDDIO0 IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VSS IO IO IO IO IO IO IO IO VDDIO7 IO IO IO ORT8850L VSS VDD33 PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N VDDIO0 PL2D PL2C VSS PL2B PL2A PL3D PL3C VDDIO0 PL3B PL3A PL4D PL4C VSS PL4B PL4A PL5D PL5C VDDIO0 PL5B PL5A PL6D PL6C VSS PL6B PL6A PL7D PL7C PL7B PL7A PL8D PL8C VDDIO7 PL8B PL8A PL9D ORT8850H VSS VDD33 PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N VDDIO0 PL2D PL2C VSS PL3D PL3C PL4D PL4C VDDIO0 PL5D PL5C PL6D PL6C VSS PL7D PL7C PL8D PL8C VDDIO0 PL9D PL9C PL10D PL10C VSS PL11D PL11C PL12D PL12C PL13D PL13C PL14D PL14C VDDIO7 PL15D PL15C PL16D Additional Function -- -- RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N -- PLL_CK0C/HPPLL PLL_CK0T/HPPLL -- -- VREF_0_07 D5 D6 -- -- VREF_0_08 HDC LDC_N -- -- -- TESTCFG D7 -- VREF_0_09 A17/PPC_A31 CS0_N CS1 -- -- -- INIT_N DOUT VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 -- -- -- VREF_7_01 Pair -- -- -- -- -- -- -- L21C_D2 L21T_D2 -- L22C_D0 L22T_D0 L23C_D0 L23T_D0 -- L24C_D0 L24T_D0 L25C_D1 L25T_D1 -- L26C_D2 L26T_D2 L27C_D0 L27T_D0 -- L28C_D0 L28T_D0 L29C_D3 L29T_D3 -- L30C_D0 L30T_D0 L31C_D0 L31T_D0 L32C_D0 L32T_D0 L1C_D0 L1T_D0 -- L2C_D0 L2T_D0 L3C_D3 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 N5 AM22 L2 N4 P5 M2 M3 M1 P4 N2 P3 AM32 R4 N1 P2 P1 T4 R2 U5 R1 AN1 V5 T3 T2 T1 R3 U4 U3 AN2 U2 V2 AN33 V3 V4 W5 W2 W3 Y1 Y2 AA1 AN34 Y5 VDDIO VREF Bank Group 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 1 -- 2 2 2 2 -- 2 2 3 3 -- 3 3 3 3 3 3 4 4 -- 4 4 4 4 -- 4 4 -- 5 5 -- 5 5 5 5 5 5 6 6 -- 6 I/O IO VSS IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO VSS IO IO VSS IO IO IO IO IO IO IO IO VSS IO ORT8850L PL9C VSS PL9B PL9A PL10D PL10C VDDIO7 PL10B PL10A PL11D PL11C VSS PL11B PL11A PL12D PL12C PL12B PL12A PL13D PL13C VSS PL13B PL13A PL14D PL14C VDDIO7 PL14B PL14A VSS PL15D PL15C VSS PL15B PL15A PL16D PL16C PL16B PL16A PL17D PL17C VSS PL17B ORT8850H PL16C VSS PL17D PL17C PL18D PL18C VDDIO7 PL19D PL19C PL20D PL20C VSS PL21D PL21C PL22D PL22C PL22B PL22A PL23D PL23C VSS PL23B PL23A PL24D PL24C VDDIO7 PL24B PL24A VSS PL25D PL25C VSS PL25B PL25A PL26D PL26C PL27D PL27C PL28D PL28C VSS PL29D Additional Function D4 -- -- -- RDY/BUSY_N/RCLK VREF_7_02 -- A13/PPC_A27 A12/PPC_A26 -- -- -- A11/PPC_A25 VREF_7_03 -- -- -- -- RD_N/MPI_STRB_N VREF_7_04 -- -- -- PLCK0C PLCK0T -- -- -- -- A10/PPC_A24 A9/PPC_A23 -- -- -- A8/PPC_A22 VREF_7_05 -- -- PLCK1C PLCK1T -- VREF_7_06 Pair L3T_D3 -- L4C_D1 L4T_D1 L5C_D2 L5T_D2 -- L6C_D2 L6T_D2 L7C_D0 L7T_D0 -- L8C_D2 L8T_D2 L9C_A0 L9T_A0 L10C_D1 L10T_D1 L11C_D3 L11T_D3 -- L12C_D1 L12T_D1 L13C_A0 L13T_A0 -- L14C_A0 L14T_A0 -- L15C_A0 L15T_A0 -- L16C_A0 L16T_A0 L17C_A2 L17T_A2 L18C_D1 L18T_D1 L19C_D0 L19T_D0 -- L20C_D3 89 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 AB1 AA5 AA3 U1 AB2 AA4 AC1 AB5 AC2 AB4 AC5 W1 AD2 AE1 AD3 AE2 AF1 AD4 AE3 AF2 AB13 AE4 AF3 AE5 AG2 AK5 AH1 AF5 AF4 AG3 AB14 AH2 AJ1 AG4 AG5 AL3 AH3 AK1 AJ2 AH5 AB15 AH4 90 VDDIO VREF Bank Group 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 6 6 -- 7 7 7 7 7 8 8 -- 8 8 8 8 8 8 1 1 -- 1 1 2 2 -- 2 2 3 3 -- 3 3 3 3 -- 4 4 4 4 -- 4 I/O IO IO IO VDDIO7 IO IO IO IO IO IO IO VDDIO7 IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO IO VSS IO ORT8850L PL17A PL18D PL18C VDDIO7 PL18B PL19D PL19C PL19B PL19A PL20D PL20C VDDIO7 PL20B PL20A PL21D PL21C PL21B PL21A PL22D PL22C VSS PL22B PL22A PL23D PL23C VDDIO6 PL23B PL23A PL24D PL24C VSS PL24B PL24A PL25D PL25C VDDIO6 PL25B PL25A PL26D PL26C VSS PL26B ORT8850H PL29C PL30D PL30C VDDIO7 PL31D PL32D PL32C PL33D PL33C PL34D PL34C VDDIO7 PL35D PL35C PL36D PL36C PL37D PL37C PL38D PL38C VSS PL39D PL39C PL40D PL40C VDDIO6 PL41D PL41C PL42D PL42C VSS PL43D PL43C PL44D PL44C VDDIO6 PL44B PL45A PL45D PL45C VSS PL46D Additional Function A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 -- -- WR_N/MPI_RW VREF_7_07 -- -- A4/PPC_A18 VREF_7_08 -- A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 -- D9 D10 -- VREF_6_02 -- -- -- D11 D12 -- -- -- VREF_6_03 D13 -- -- -- -- VREF_6_04 -- -- Pair L20T_D3 L21C_A1 L21T_A1 -- -- L22C_D2 L22T_D2 L23C_D2 L23T_D2 L23C_D0 L23T_D0 -- L23C_D0 L23T_D0 L24C_D0 L24T_D0 L25C_D2 L25T_D2 L1C_D0 L1T_D0 -- L2C_D0 L2T_D0 L3C_D1 L3T_D1 -- L4C_D3 L4T_D3 L5C_D0 L5T_D0 -- L6C_D0 L6T_D0 L7C_A0 L7T_A0 -- -- -- L8C_D2 L8T_D2 -- -- Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 AJ3 AK2 AL1 AB20 AJ5 AJ4 AB21 AK3 AM1 AL2 AK4 AB22 AK6 AL5 AN4 AM2 AM5 AK7 AL6 AN5 AM4 AM6 AL7 AK8 AP5 AB32 AK9 AN6 AM7 AP6 AN3 AL8 AN7 AM8 AL9 AL4 AP7 AN8 AL10 AP8 AL11 AM10 VDDIO VREF Bank Group 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) -- -- 6 (BL) -- -- -- -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 4 4 4 -- 4 4 -- -- -- -- -- -- -- 5 5 -- 5 5 5 5 -- 5 5 6 6 -- 6 6 6 6 -- 7 7 7 7 -- 7 7 8 8 8 8 I/O IO IO IO VSS IO IO VSS I VDDIO6 IO VDD33 VSS VDD33 IO IO VDDIO6 IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO IO IO ORT8850L PL26A PL27D PL27C VSS PL27B PL27A VSS PTEMP VDDIO6 LVDS_R VDD33 VSS VDD33 PB2A PB2B VDDIO6 PB2C PB2D PB3A PB3B VDDIO6 PB3C PB3D PB4A PB4B VSS PB4C PB4D PB5A PB5B VDDIO6 PB5C PB5D PB6A PB6B VSS PB6C PB6D PB7A PB7B PB7C PB7D ORT8850H PL46A PL47D PL47C VSS PL47B PL47A VSS PTEMP VDDIO6 LVDS_R VDD33 VSS VDD33 PB2A PB2B VDDIO6 PB2C PB2D PB3C PB3D VDDIO6 PB4C PB4D PB5C PB5D VSS PB6C PB6D PB7C PB7D VDDIO6 PB8C PB8D PB9C PB9D VSS PB10C PB10D PB11C PB11D PB12C PB12D Additional Function -- PLL_CK7C/HPPLL PLL_CK7T/HPPLL -- -- -- -- PTEMP -- LVDS_R -- -- -- DP2 -- -- PLL_CK6T/PPLL PLL_CK6C/PPLL -- -- -- VREF_6_05 DP3 -- -- -- VREF_6_06 D14 -- -- -- D15 D16 D17 D18 -- VREF_6_07 D19 D20 D21 VREF_6_08 D22 Pair -- L9C_D0 L9T_D0 -- L10C_A0 L10T_A0 -- -- -- -- -- -- -- L11T_D1 L11C_D1 -- L12T_D1 L12C_D1 L13T_D1 L13C_D1 -- L14T_D0 L14C_D0 L15T_D3 L15C_D3 -- L16T_D2 L16C_D2 L17T_D1 L17C_D1 -- L18T_D1 L18C_D1 L19T_D0 L19C_D0 -- L20T_D0 L20C_D0 L21T_D2 L21C_D2 L22T_D0 L22C_D0 91 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 AK12 AP9 AL31 AN10 AL12 AM11 AP10 AP3 AK13 AN11 AL13 AK14 AM3 AN12 AL14 AP12 AN13 AP13 AK15 AL15 AK16 AM13 AP14 AL16 AN15 AP15 AK17 Y15 AM16 AN16 AL17 AM12 AP16 AM17 AN17 AL18 AN18 AM18 AN19 AK18 Y20 AM19 92 VDDIO VREF Bank Group 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 9 9 -- 9 9 9 9 -- 9 9 9 9 -- 10 10 10 10 10 10 11 11 -- 11 11 1 1 1 -- 1 1 1 -- 2 2 2 2 2 2 2 2 -- 2 I/O IO IO VSS IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO IO IO IO IO VSS IO IO IO IO IO VSS IO IO IO VDDIO5 IO IO IO IO IO IO IO IO VSS IO ORT8850L PB8A PB8B VSS PB8C PB8D PB9A PB9B VDDIO6 PB9C PB9D PB10A PB10B VSS PB10C PB10D PB11A PB11B PB11C PB11D PB12A PB12B VSS PB12C PB12D PB13C PB14A PB14B VSS PB14C PB15A PB15B VDDIO5 PB15C PB15D PB16A PB16B PB16C PB16D PB17A PB17B VSS PB17C ORT8850H PB13A PB13B VSS PB13C PB13D PB14A PB14B VDDIO6 PB14C PB14D PB15C PB15D VSS PB16C PB16D PB17C PB17D PB18C PB18D PB19C PB19D VSS PB20C PB20D PB21A PB21C PB21D VSS PB22A PB22C PB22D VDDIO5 PB23A PB23B PB23C PB23D PB24A PB24B PB24C PB24D VSS PB25C Additional Function -- -- -- D23 D24 -- -- -- VREF_6_09 D25 -- -- -- D26 D27 -- -- VREF_6_10 D28 D29 D30 -- VREF_6_11 D31 -- -- -- -- -- VREF_5_01 -- -- -- -- PBCK0T PBCK0C -- -- VREF_5_02 -- -- -- Pair L23T_D3 L23C_D3 -- L24T_D1 L24C_D1 L25T_D1 L25C_D1 -- L26T_D2 L26C_D2 L27T_D0 L27C_D0 -- L28T_D1 L28C_D1 L29T_D0 L29C_D0 L30T_D3 L30C_D3 L31T_D0 L31C_D0 -- L32T_D2 L32C_D2 -- L1T_D3 L1C_D3 -- -- L2T_D1 L2C_D1 -- L3T_D1 L3C_D1 L4T_D1 L4C_D1 L5T_A0 L5C_A0 L6T_D2 L6C_D2 -- L7T_A0 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 AL19 AP20 AK19 AM15 AN20 Y21 AP21 AL20 Y22 AK20 AN21 AM21 AM20 AK21 AP22 AL21 AA15 AN22 AP23 AN23 AA13 AK22 AL22 AN24 AK23 AA14 AL23 AM24 AP25 AN25 AP26 AK25 AN26 AP27 AM25 AK26 N32 AL24 AK24 A32 AN27 AP28 VDDIO VREF Bank Group 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- -- -- -- -- -- 2 3 3 -- 3 -- 3 3 -- 3 3 3 -- 3 4 4 -- 4 4 4 -- 4 4 5 5 -- 5 5 5 5 6 6 6 6 6 6 -- -- -- -- -- -- I/O IO IO IO VDDIO5 IO VSS IO IO VSS IO IO IO VDDIO5 IO IO IO VSS IO IO IO VSS IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO VSS O O VDD33 O O ORT8850L PB17D PB18A PB18B VDDIO5 PB18C VSS PB19A PB19B VSS PB19C PB20A PB20B VDDIO5 PB20C PB21A PB21B VSS PB21C PB22A PB22B VSS PB22C PB22D PB23C PB23D VSS PB24C PB24D PB25A PB25B PB25C PB26A PB26B PB26C PB27A PB27B VSS TXD_C0_N TXD_C0_P VDD33 TXD_C1_N TXD_C1_P ORT8850H PB25D PB26C PB26D VDDIO5 PB27A VSS PB27C PB27D VSS PB28A PB28C PB28D VDDIO5 PB29A PB29C PB29D VSS PB30A PB30C PB30D VSS PB31C PB31D PB32C PB32D VSS PB33C PB33D PB34C PB34D PB35A PB35C PB35D PB36A PB36C PB36D VSS TXD_C0_N TXD_C0_P VDD33 TXD_C1_N TXD_C1_P Additional Function -- -- VREF_5_03 -- -- -- -- -- -- -- PBCK1T PBCK1C -- -- -- -- -- -- -- VREF_5_04 -- -- -- -- VREF_5_05 -- -- -- -- -- -- -- VREF_5_06 -- -- -- -- -- -- -- -- -- Pair L7C_A0 L8T_D3 L8C_D3 -- -- -- L9T_D2 L9C_D2 -- -- L10T_A0 L10C_A0 -- -- L11T_D2 L11C_D2 -- -- L12T_A0 L12C_A0 -- L13T_A0 L13C_A0 L14T_D2 L14C_D2 -- L15T_D0 L15C_D0 L16T_A0 L16T_A0 -- L17T_A0 L17C_A0 -- L18T_D3 L18C_D3 -- L1N_A0 L1P_A0 -- L2N_D0 L2P_D0 93 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 P13 AL25 AL26 B32 AM26 AM27 P14 AN28 AP29 C31 AL27 AK27 P15 AL28 AK28 C33 AM28 AN29 P20 AL29 AK29 C34 AP30 AN30 P21 AM29 AP31 D32 AM30 AN31 P22 R13 R14 E30 AL30 E31 AH30 AJ30 R15 AL33 AH31 L34 94 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VSS O O VDD33 O O VSS O O VDD33 O O VSS O O VDD33 O O VSS O O VDD33 O O VSS I I VDD33 I I VSS VSS VSS VDD33 I VDD33 I I VSS I I VDD33 ORT8850L VSS TXD_C2_N TXD_C2_P VDD33 TXD_C3_N TXD_C3_P VSS TXSOC_C_N TXSOC_C_P VDD33 TXCLK_C_N TXCLK_C_P VSS TXD_C4_N TXD_C4_P VDD33 TXD_C5_N TXD_C5_P VSS TXD_C6_N TXD_C6_P VDD33 TXD_C7_N TXD_C7_P VSS DAUTREC TSTCLK VDD33 TESTRST TSTSHFTLD VSS VSS VSS VDD33 RESETTX VDD33 ETOGGLE ECSEL VSS EXDNUP MRESET VDD33 ORT8850H VSS TXD_C2_N TXD_C2_P VDD33 TXD_C3_N TXD_C3_P VSS TXSOC_C_N TXSOC_C_P VDD33 TXCLK_C_N TXCLK_C_P VSS TXD_C4_N TXD_C4_P VDD33 TXD_C5_N TXD_C5_P VSS TXD_C6_N TXD_C6_P VDD33 TXD_C7_N TXD_C7_P VSS DAUTREC TSTCLK VDD33 TESTRST TSTSHFTLD VSS VSS VSS VDD33 RESETTX VDD33 ETOGGLE ECSEL VSS EXDNUP MRESET VDD33 Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair -- L3N_A0 L3P_A0 -- L4N_A0 L4P_A0 -- L5N_D0 L5P_D0 -- L6N_A0 L6P_A0 -- L7N_A0 L7P_A0 -- L8N_D0 L8P_D0 -- L9N_A0 L9P_A0 -- L10N_D0 L10P_D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 AK32 AJ31 R20 AL34 AK33 AJ32 M32 AF30 AG30 R21 AG31 AF31 AK34 R32 AJ33 AH32 R22 AJ34 AH33 AD30 U34 AG32 AG33 T16 AH34 AE30 AE31 W34 AF32 AF33 T17 AC30 AG34 AF34 Y32 AB30 AD31 T18 AE32 AE33 AC32 AE34 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O I I VSS I I I VDD33 I I VSS I I I VDD33 I I VSS I I I VDD33 I I VSS I I I VDD33 I I VSS I I I VDD33 VDDA_STM VSSA_STM VSS I I VDD33 I ORT8850L RXD_C0_N RXD_C0_P VSS RXD_C1_N RXD_C1_P LVCTAP_C_0 VDD33 RXD_C2_N RXD_C2_P VSS RXD_C3_N RXD_C3_P LVCTAP_C_1 VDD33 RXSOC_C_N RXSOC_C_P VSS RXCLK_C_N RXCLK_C_P LVCTAP_C_2 VDD33 RXD_C4_N RXD_C4_P VSS LVCTAP_C_3 RXD_C5_N RXD_C5_P VDD33 RXD_C6_N RXD_C6_P VSS LVCTAP_C_4 RXD_C7_N RXD_C7_P VDD33 VDDA_STM VSSA_STM VSS SYS_CLK_N SYS_CLK_P VDD33 LVCTAP_SK ORT8850H RXD_C0_N RXD_C0_P VSS RXD_C1_N RXD_C1_P LVCTAP_C_0 VDD33 RXD_C2_N RXD_C2_P VSS RXD_C3_N RXD_C3_P LVCTAP_C_1 VDD33 RXSOC_C_N RXSOC_C_P VSS RXCLK_C_N RXCLK_C_P LVCTAP_C_2 VDD33 RXD_C4_N RXD_C4_P VSS LVCTAP_C_3 RXD_C5_N RXD_C5_P VDD33 RXD_C6_N RXD_C6_P VSS LVCTAP_C_4 RXD_C7_N RXD_C7_P VDD33 VDDA_STM VSSA_STM VSS SYS_CLK_N SYS_CLK_P VDD33 LVCTAP_SK Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair L11N_D0 L11P_D0 -- L12N_D0 L12P_D0 -- -- L13N_A0 L13P_A0 -- L14N_A0 L14P_A0 -- -- L15N_A0 L15P_A0 -- L16N_D0 L16P_D0 -- -- L17N_A0 L17P_A0 -- -- L18N_A0 L18P_A0 -- L19N_A0 L19P_A0 -- -- L20N_A0 L20P_A0 -- -- -- -- L21N_D0 L21P_D0 -- -- 95 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 T19 AC31 AB31 T34 AD32 AD33 AA30 AD34 AC33 AC34 U16 AB33 AB34 Y30 AK30 AA31 AA32 U17 W30 Y31 AA33 AK31 AA34 Y34 U18 Y33 W31 W32 AL32 V30 V31 U19 W33 V32 V33 V1 U33 U32 U31 T33 AM31 V16 96 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VSS I I VSS I I I VDD33 I I VSS I I I VDD33 I I VSS I I I VDD33 I I VSS I I I VDD33 I I VSS I I I VSS I I I I VDD33 VSS ORT8850L VSS RXD_B0_N RXD_B0_P VSS RXD_B1_N RXD_B1_P LVCTAP_B_0 VDD33 RXD_B2_N RXD_B2_P VSS RXD_B3_N RXD_B3_P LVCTAP_B_1 VDD33 RXSOC_B_N RXSOC_B_P VSS RXCLK_B_N RXCLK_B_P LVCTAP_B_2 VDD33 RXD_B4_N RXD_B4_P VSS LVCTAP_B_3 RXD_B5_N RXD_B5_P VDD33 RXD_B6_N RXD_B6_P VSS LVCTAP_B_4 RXD_B7_N RXD_B7_P VSS RESLO RESHI REF14 REF10 VDD33 VSS ORT8850H VSS RXD_B0_N RXD_B0_P VSS RXD_B1_N RXD_B1_P LVCTAP_B_0 VDD33 RXD_B2_N RXD_B2_P VSS RXD_B3_N RXD_B3_P LVCTAP_B_1 VDD33 RXSOC_B_N RXSOC_B_P VSS RXCLK_B_N RXCLK_B_P LVCTAP_B_2 VDD33 RXD_B4_N RXD_B4_P VSS LVCTAP_B_3 RXD_B5_N RXD_B5_P VDD33 RXD_B6_N RXD_B6_P VSS LVCTAP_B_4 RXD_B7_N RXD_B7_P VSS RESLO RESHI REF14 REF10 VDD33 VSS Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair -- L22N_A0 L22P_A0 -- L23N_A0 L23P_A0 -- -- L24N_A0 L24P_A0 -- L25N_A0 L25P_A0 -- -- L26N_A0 L26P_A0 -- L27N_D0 L27P_D0 -- -- L28N_A0 L28P_A0 -- -- L29N_A0 L29P_A0 -- L30N_A0 L30P_A0 -- -- L31N_A0 L31P_A0 -- -- -- -- -- -- -- Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 T32 R34 AM33 U30 T31 V17 R33 P34 AM34 P33 N34 V18 T30 R31 AN32 P32 R30 V19 N33 M34 AP32 P31 M33 V34 N31 P30 L33 K34 W16 M31 L32 K33 W17 N30 L30 W18 M30 L31 W19 J34 K32 J33 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O O O VDD33 O O VSS O O VDD33 O O VSS O O VDD33 O O VSS O O VDD33 O O VSS O O O O VSS I I I VSS VDDA_SHIM VSSA_SHIM VSS I I VSS I I I ORT8850L TXD_B0_N TXD_B0_P VDD33 TXD_B1_N TXD_B1_P VSS TXD_B2_N TXD_B2_P VDD33 TXD_B3_N TXD_B3_P VSS TXSOC_B_N TXSOC_B_P VDD33 TXCLK_B_N TXCLK_B_P VSS TXD_B4_N TXD_B4_P VDD33 TXD_B5_N TXD_B5_P VSS TXD_B6_N TXD_B6_P TXD_B7_N TXD_B7_P VSS GCLK_N GCLK_P LVCTAP_GK VSS VDDA_SHIM VSSA_SHIM VSS RXD_A0_N RXD_A0_P VSS RXD_A1_N RXD_A1_P LVCTAP_A_0 ORT8850H TXD_B0_N TXD_B0_P VDD33 TXD_B1_N TXD_B1_P VSS TXD_B2_N TXD_B2_P VDD33 TXD_B3_N TXD_B3_P VSS TXSOC_B_N TXSOC_B_P VDD33 TXCLK_B_N TXCLK_B_P VSS TXD_B4_N TXD_B4_P VDD33 TXD_B5_N TXD_B5_P VSS TXD_B6_N TXD_B6_P TXD_B7_N TXD_B7_P VSS GCLK_N GCLK_P LVCTAP_GK VSS VDDA_SHIM VSSA_SHIM VSS RXD_A0_N RXD_A0_P VSS RXD_A1_N RXD_A1_P LVCTAP_A_0 Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair L32N_D1 L32P_D1 -- L33N_D0 L33P_D0 -- L34N_D0 L34P_D0 -- L35N_D0 L35P_D0 -- L36N_D0 L36P_D0 -- L37N_D1 L37P_D1 -- L38N_D0 L38P_D0 -- L39N_D1 L39P_D1 -- L40N_D0 L40P_D0 L41N_D0 L41P_D0 -- L42N_D0 L42P_D0 -- -- -- -- -- L43N_D0 L43P_D0 -- L44N_D1 L44P_D1 -- 97 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 H34 J32 Y13 K31 K30 H33 J31 J30 Y14 G34 H32 H31 G33 F34 H30 G32 F33 G30 G31 E34 F32 E33 F31 E32 D34 D33 F30 D30 E29 C30 B31 D29 B30 A31 B29 E28 C29 D28 E27 A30 C28 B28 98 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O I I VSS I I I I I VSS I I I I I I I I I I I I I O O O O O O O O O O I I I O O O O O O O ORT8850L ORT8850H Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair L45N_D1 L45P_D1 -- L46N_A0 L46P_A0 -- L47N_A0 L47P_A0 -- L48N_D1 L48P_D1 -- L49N_D0 L49P_D0 -- L50N_D0 L50P_D0 L51N_A0 L51P_A0 -- L52N_A0 L52P_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- L53N_D1 L53P_D1 L54N_D0 L54P_D0 L55N_D1 L55P_D1 L56N_D0 Agere Systems Inc. RXD_A2_N RXD_A2_N RXD_A2_P RXD_A2_P VSS VSS RXD_A3_N RXD_A3_N RXD_A3_P RXD_A3_P LVCTAP_A_1 LVCTAP_A_1 RXSOC_A_N RXSOC_A_N RXSOC_A_P RXSOC_A_P VSS VSS RXCLK_A_N RXCLK_A_N RXCLK_A_P RXCLK_A_P LVCTAP_A_2 LVCTAP_A_2 RXD_A4_N RXD_A4_N RXD_A4_P RXD_A4_P LVCTAP_A_3 LVCTAP_A_3 RXD_A5_N RXD_A5_N RXD_A5_P RXD_A5_P RXD_A6_N RXD_A6_N RXD_A6_P RXD_A6_P LVCTAP_A_4 LVCTAP_A_4 RXD_A7_N RXD_A7_N RXD_A7_P RXD_A7_P TSTMUX0S TSTMUX0S TSTMUX1S TSTMUX1S TSTMUX2S TSTMUX2S TSTMUX3S TSTMUX3S TSTMUX4S TSTMUX4S TSTMUX5S TSTMUX5S TSTMUX6S TSTMUX6S TSTMUX7S TSTMUX7S TSTMUX8S TSTMUX8S TSTMUX9S TSTMUX9S SCANEN SCANEN SCAN_TSTMD SCAN_TSTMD RST_N RST_N TXD_A0_N TXD_A0_N TXD_A0_P TXD_A0_P TXD_A1_N TXD_A1_N TXD_A1_P TXD_A1_P TXD_A2_N TXD_A2_N TXD_A2_P TXD_A2_P TXD_A3_N TXD_A3_N Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 A29 D27 E26 C27 D26 A28 B27 C26 D25 A27 B26 D24 C25 C22 A26 E25 A25 B25 C24 D23 C32 B24 E24 D22 B23 E23 A23 D21 B22 D4 A22 C21 E22 D20 B21 D31 E21 A21 B20 A11 A20 E20 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 -- 1 1 2 2 2 2 2 2 -- 3 3 3 3 3 -- 3 3 3 -- 3 4 I/O O O O O O O O O O O O O O VSS IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO VSS IO IO IO IO IO VSS IO IO IO VDDIO1 IO IO ORT8850L TXD_A3_P TXSOC_A_N TXSOC_A_P TXCLK_A_N TXCLK_A_P TXD_A4_N TXD_A4_P TXD_A5_N TXD_A5_P TXD_A6_N TXD_A6_P TXD_A7_N TXD_A7_P VSS PT26D PT26C PT26B PT26A PT25D PT25C VSS PT25B PT25A PT24D PT24C PT24B PT24A PT23D PT23C VSS PT22D PT22C PT22A PT21D PT21C VSS PT21A PT20D PT20C VDDIO1 PT20A PT19D ORT8850H TXD_A3_P TXSOC_A_N TXSOC_A_P TXCLK_A_N TXCLK_A_P TXD_A4_N TXD_A4_P TXD_A5_N TXD_A5_P TXD_A6_N TXD_A6_P TXD_A7_N TXD_A7_P VSS PT35D PT35C PT35B PT35A PT34D PT34C VSS PT33D PT33C PT32D PT32C PT31D PT31C PT30D PT30C VSS PT29D PT29C PT29A PT28D PT28C VSS PT28A PT27D PT27C VDDIO1 PT27A PT26D Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_01 -- -- -- -- -- VREF_1_02 -- -- -- -- -- -- VREF_1_03 -- -- -- -- -- -- -- -- -- -- Pair L56P_D0 L57N_D0 L57P_D0 L58N_D0 L58P_D0 L59N_D0 L59P_D0 L60N_D0 L60P_D0 L61N_D0 L61P_D0 L62N_D0 L62P_D0 -- L1C_D3 L1T_D3 L2C_A0 L2T_A0 L3C_D0 L3T_D0 -- L4C_A2 L4T_A2 L5C_D1 L5T_D1 L6C_A3 L6T_A3 L7C_D1 L7T_D1 -- L8C_D1 L8T_D1 -- L9C_D1 L9T_D1 -- -- L10C_D0 L10T_D0 -- -- L11C_D0 99 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 D19 C19 B19 N3 E19 D18 A17 B18 C18 B17 C17 N13 A16 D17 B16 C16 D16 E18 A15 A19 B15 D15 A14 N14 B14 E17 C14 D14 N15 E16 A13 B13 A12 B12 D13 A34 E15 B11 A10 E14 A3 D12 100 VDDIO VREF Bank Group 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 4 4 4 -- 4 4 -- 4 4 5 5 -- 5 5 5 5 5 5 5 -- 5 6 6 -- 6 6 6 6 -- 1 1 1 1 1 1 -- 2 2 2 2 -- 2 I/O IO IO IO VSS IO IO VDDIO1 IO IO IO IO VSS IO IO IO IO IO IO IO VDDIO1 IO IO IO VSS IO IO IO IO VSS IO IO IO IO IO IO VSS IO IO IO IO VDDIO0 IO ORT8850L PT19C PT19B PT19A VSS PT18D PT18C VDDIO1 PT18B PT18A PT17D PT17C VSS PT17B PT17A PT16D PT16C PT16A PT15D PT15C VDDIO1 PT15A PT14D PT14C VSS PT14A PT13D PT13C PT13A VSS PT11D PT11C PT11B PT11A PT10D PT10C VSS PT10B PT10A PT9D PT9C VDDIO0 PT9B ORT8850H PT26C PT25D PT25C VSS PT24D PT24C VDDIO1 PT24B PT24A PT23D PT23C VSS PT23B PT23A PT22D PT22C PT22A PT21D PT21C VDDIO1 PT21A PT20D PT20C VSS PT20A PT19D PT19C PT19A VSS PT18D PT18C PT17D PT17C PT16D PT16C VSS PT15D PT15C PT14D PT14C VDDIO0 PT13D Additional Function -- -- -- -- -- VREF_1_04 -- -- -- PTCK1C PTCK1T -- -- -- PTCK0C PTCK0T -- VREF_1_05 -- -- -- -- -- -- -- -- VREF_1_06 -- -- MPI_RTRY_N MPI_ACK_N -- VREF_0_01 M0 M1 -- MPI_CLK A21/MPI_BURST_N M2 M3 -- VREF_0_02 Pair L11T_D0 L12C_A0 L12T_A0 -- L13C_D0 L13T_D0 -- L14C_A0 L14T_A0 L15C_A0 L15T_A0 -- L16C_D2 L16T_D2 L17C_A0 L17T_A0 -- L18C_D3 L18T_D3 -- -- L19C_D2 L19T_D2 -- -- L20C_D2 L20T_D2 -- -- L1C_D3 L1T_D3 L2C_D0 L2T_D0 L3C_D1 L3T_D1 -- L4C_D3 L4T_D3 L5C_D3 L5T_D3 -- L6C_D0 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 C11 B10 A9 C10 B9 A8 D10 B1 C9 B8 A7 E12 B3 D9 C8 E11 B7 B2 A6 D8 C7 A5 C1 E10 D7 A4 E9 B33 B6 C6 B5 D6 C2 C5 B4 E8 E7 D5 E6 B34 A24 AM23 VDDIO VREF Bank Group 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- -- -- -- -- 1 (TC) 5 (BC) 2 3 3 3 3 3 3 -- 4 4 4 4 -- 4 4 5 5 -- 5 5 5 5 -- 5 5 6 6 -- 6 6 6 6 -- 6 6 -- -- -- -- -- -- -- I/O IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO O IO IO VDD33 VSS VDDIO1 VDDIO5 ORT8850L PT9A PT8D PT8C PT8B PT8A PT7D PT7C VSS PT7B PT7A PT6D PT6C VDDIO0 PT6B PT6A PT5D PT5C VSS PT5B PT5A PT4D PT4C VDDIO0 PT4B PT4A PT3D PT3C VSS PT3B PT3A PT2D PT2C VDDIO0 PT2B PT2A PCCLK PDONE VDD33 VSS VDDIO1 VDDIO5 ORT8850H PT13C PT12D PT12C PT11D PT11C PT10D PT10C VSS PT9D PT9C PT8D PT8C VDDIO0 PT7D PT7C PT6D PT6C VSS PT5D PT5C PT4D PT4C VDDIO0 PT4B PT4A PT3D PT3C VSS PT3B PT3A PT2D PT2C VDDIO0 PT2B PT2A PCCLK PDONE VDD33 VSS VDDIO1 VDDIO5 Additional Function MPI_TEA_N -- -- VREF_0_03 -- D0 TMS -- A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 -- VREF_0_04 -- D1 D2 -- -- VREF_0_05 TDI TCK -- -- -- -- VREF_0_06 -- -- -- PLL_CK1C/PPLL PLL_CK1T/PPLL -- -- -- CFG_IRQ_N/MPI_IRQ_N Pair L6T_D0 L7C_D0 L7T_D0 L8C_D0 L8T_D0 L9C_D2 L9T_D2 -- L10C_D0 L10T_D0 L11C_D4 L11T_D4 -- L12C_D0 L12T_D0 L13C_D3 L13T_D3 -- L14C_D2 L14T_D2 L15C_D1 L15T_D1 -- L16C_D2 L16T_D2 L17C_D4 L17T_D4 -- L18C_A0 L18T_A0 L19C_D1 L19T_D1 -- L20C_D0 L20T_D0 -- -- -- -- -- -- -- 101 PCFG_MPI_IRQ PCFG_MPI_IRQ CCLK DONE -- -- -- -- Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 AP1 K4 M5 R5 T5 W4 AA2 Y4 AC4 AD5 AG1 AK10 AK11 AM9 AN9 AM14 AN14 D11 E13 AP4 Y3 AC3 AD1 AP11 AP17 AP19 AP24 C12 C15 C20 C23 W22 Y16 V22 U22 T22 P17 P18 N16 N17 N18 N19 102 VDDIO VREF Bank Group -- 0 (TL) 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 0 (TL) 0 (TL) 6 (BL) 7 (CL) 7 (CL) 7 (CL) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- -- -- -- -- -- -- -- -- -- -- -- 10 10 3 3 5 6 6 8 8 1 7 7 8 8 11 11 3 3 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VSS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VDDIO7 VDDIO7 VDDIO7 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 ORT8850L VSS UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED VDDIO7 VDDIO7 VDDIO7 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 ORT8850H VSS PL11A PL13A PL20A PL21A PL27A PL28A PL29A PL35A PL37A PL38A PB9A PB10A PB11A PB12A PB19A PB20A PT12A PT11A PB3A VDDIO7 VDDIO7 VDDIO7 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 P16 P19 R16 R17 R18 R19 T13 T14 T15 T20 T21 U13 U14 U15 U20 U21 V13 V14 V15 V20 V21 W13 W14 W15 W20 W21 Y17 Y18 Y19 AA16 AA17 AA18 AA19 AB16 AB17 AB18 C3 C13 AP2 AP18 AP33 AP34 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VSS VSS VSS VSS VSS VSS ORT8850L VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VSS VSS VSS VSS VSS VSS ORT8850H VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VSS VSS VSS VSS VSS VSS Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 103 Agere Systems Inc. ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued) BM680 AA20 AA21 AA22 N21 N22 AB3 AB19 N20 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VSS VSS VSS VSS VSS VSS VDD15 VSS ORT8850L VSS VSS VSS VSS VSS VSS VDD15 VSS ORT8850H VSS VSS VSS VSS VSS VSS VDD15 VSS Additional Function -- -- -- -- -- -- -- -- Pair -- -- -- -- -- -- -- -- 104 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver JC This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by: TJ - TC JC = ------------------Q Package Thermal Characteristics Summary There are three thermal parameters that are in common use: JA, JC, and JC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. JA This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.). TJ - TA JA = ------------------Q The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a watercooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/W. where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/watt. JB This is the thermal resistance from junction to board (JL). It is defined by: TJ - TB JB = ------------------Q where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that JB is expressed in units of C/W and that this parameter and the way it is measured are still in JEDEC committee. JC This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance, and it is defined by: TJ - TC JC = ------------------Q FPSC Maximum Junction Temperature Once the power dissipated by the FPSC has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q * JA) Table 35 lists the thermal characteristics for all packages used with the ORCA ORT8850 Series of FPSCs. where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/W. Agere Systems Inc. 105 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Package Thermal Characteristics Table 35. ORCA ORT8850 Plastic Package Thermal Guidelines Package Parasitics The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 36 lists eight parasitics associated with the ORCA packages. These parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. Resistance values are in m. The parasitic values in Table 36 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. JA (C/W) Package 352-Pin PBGA 680-Pin PBGAM* 0 fpm 19.0 13.4 200 fpm 16.0 11.5 500 fpm 15.0 10.5 T = 70 C Max, TJ = 125 C Max, 0 fpm (W) 2.90 4.10 * The 680-Pin PBGAM package includes 2 oz copper plates. Package Coplanarity The coplanarity limits of the Agere packages are as follows: s s PBGAM: 8.0 mils PBGA: 8.0 mils Table 36. ORCA ORT8850 Package Parasitics Package Type 352-Pin PBGA 680-Pin PBGAM LSW 5.0 3.8 LMW 2.0 1.3 RW 220 250 C1 1.5 1.0 C2 1.5 1.0 CM 1.5 0.3 LSL LML 7.0--12.0 3.0--6.0 2.8--5.0 0.5--1.0 LSW PAD N RW LSL CIRCUIT BOARD PAD C1 LMW CM LML C2 PAD N + 1 LSW RW C1 LSL C2 5-3862(C)r2 Figure 25. Package Parasitics 106 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Package Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension. Agere Systems Inc. 107 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Package Outline Drawings 352-Pin PBGA Dimensions are in millimeters. 35.00 0.20 A1 BALL IDENTIFIER ZONE +0.70 30.00 -0.00 30.00 +0.70 -0.00 35.00 0.20 MOLD COMPOUND PWB 0.56 0.06 1.17 0.05 2.33 0.21 SEATING PLANE 0.20 0.60 0.10 SOLDER BALL 25 SPACES @ 1.27 = 31.75 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 25 0.75 0.15 25 SPACES @ 1.27 = 31.75 CENTER ARRAY FOR THERMAL ENHANCEMENT (OPTIONAL) (SEE NOTE BELOW) A1 BALL CORNER 5-4407(F) Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package. 108 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Package Outline Diagrams (continued) 680-Pin PBGAM Dimensions are in millimeters. 35.00 A1 BALL IDENTIFIER ZONE 30.00 - 0.00 + 0.70 35.00 30.00 - 0.00 + 0.70 1.170 0.61 0.08 SEATING PLANE 0.20 SOLDER BALL 0.50 0.10 33 SPACES @ 1.00 = 33.00 2.51 MAX AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 31 33 10 12 14 16 18 20 22 24 26 28 30 32 34 0.64 0.15 33 SPACES @ 1.00 = 33.00 A1 BALL CORNER 5-4406(F) Agere Systems Inc. 109 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Hardware Ordering Information ORT8850(L)(H) DEVICE TYPE SPEED GRADE -2 BM 680 TEMPERATURE RANGE NUMBER OF PINS PACKAGE TYPE 5-6435(F)p Table 37. Device Type Options Device ORT8850L Parameter Voltage Package ORT8850H Voltage Package Value 1.5 V core. 3.3 V/2.5 V I/O. 680-pin PBGAM. 352-pin PBGA. (Four channels with redundancy only.) 1.5 V core. 3.3 V/2.5 V I/O. 680-pin PBGAM. Table 38. Temperature Options Symbol (Blank) Description Industrial Temperature -40 C to +85 C Table 39. Package Type Options Symbol BM BA Description Plastic Ball Grid Array, Multilayer Plastic Ball Grid Array Table 40. ORCA FPSC Package Matrix (Speed Grades) Package Device 680-Pin PBGAM BM680 352-Pin PBGA BA352 ORT8850L ORT8850H -1, -2, -3 -1, -2, -3 -1, -2, -3 -- 110 Agere Systems Inc. Data Sheet August 2001 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Software Ordering Information Implementing a design in an ORT8850H/L requires the ORCA Foundry Development System and an ORT8850 FPSC Desgin Kit. For ordering information, please visit: http://www.agere.com/netcom/ipkits/ort8850/ Agere Systems Inc. 111 ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet August 2001 Motorola is a registered trademark and RapidIO is a trademark of Motorola, Inc. EIA is a registered trademark of Electronic Industries Association. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. PAL is a trademark of Advanced Micro Devices, Inc. PowerPC is a registered trademark of International Business Machines, Corporation. AMBA is a trademark and ARM is a registered trademark of Advanced RISC Machines Limited. Synopsys Smart Model is a registed trademark of Synopsys, Inc. For additional information, contact your Agere Systems Account Manager or the following: http://www.agere.com or for FPGAs/FPSCs: http://www.agere.com/orca INTERNET: docmaster@agere.com E-MAIL: N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) Tel. (44) 7000 624624, FAX (44) 1344 488 045 EUROPE: Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. ORCA is a registered trademark of Agere Systems Inc. Foundry is a trademark of Xilinx. Copyright (c) 2001 Agere Systems Inc. All Rights Reserved August 2001 DS01-198NCIP (Replaces DS01-094NCIP) |
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